公开(公告)号：US20150263130A1

公开(公告)日：2015-09-17

申请号：US14438824

申请日：2014-01-09

Applicant: KABUSHIKI KAISHA TOYOTA CHUO KENKYUSHO ,  TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

Inventor： Sachiko Aoi ,  Yukihiko Watanabe ,  Katsumi Suzuki ,  Shoji Mizuno

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/417 ,  H01L29/16

CPC classification number: H01L29/66348 ,  H01L29/0619 ,  H01L29/0847 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/1602 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/66045 ,  H01L29/66068 ,  H01L29/66333 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/7813

Abstract: A method of manufacturing a semiconductor device includes: forming a first trench in a first area of a drift layer that has a surface including the first area and a second area; growing a crystal of a p-type base layer on a surface of the drift layer after forming the first trench; and growing a crystal of an n-type source layer on a surface of the base layer. Material of the drift layer, the base layer, and the source layer are a wide-gap semiconductor.

Abstract translation: 一种制造半导体器件的方法包括：在漂移层的第一区域中形成具有包括第一区域和第二区域的表面的第一沟槽; 在形成第一沟槽之后，在漂移层的表面上生长p型基底层的晶体; 以及在所述基底层的表面上生长n型源极层的晶体。 漂移层，基极层和源极层的材料是宽间隙半导体。

公开(公告)号：US12205984B2

公开(公告)日：2025-01-21

申请号：US17829791

申请日：2022-06-01

Applicant: DENSO CORPORATION

Inventor： Jun Saito ,  Keita Kataoka ,  Yusuke Yamashita ,  Yukihiko Watanabe ,  Katsuhiro Kutsuki ,  Youngshin Eum

IPC: H01L29/06 ,  H01L29/739

Abstract: A semiconductor device includes a semiconductor substrate, a top electrode in contact with a top surface of the semiconductor substrate, a bottom electrode in contact with a bottom surface of the semiconductor substrate, and an oxide film in contact with the top surface of the semiconductor substrate. The semiconductor substrate includes an element region and an outer peripheral region. The element region is a region where the top electrode is in contact with the top surface of the semiconductor substrate. The outer peripheral region is a region where the oxide film is in contact with the top surface of the semiconductor substrate, and is located between the element region and an outer peripheral end surface of the semiconductor substrate. The element region includes a semiconductor element connected between the top electrode and the bottom electrode. The outer peripheral region includes surface high-voltage-breakdown regions, deep high-voltage-breakdown regions, and a drift region.

公开(公告)号：US10446649B2

公开(公告)日：2019-10-15

申请号：US14652483

申请日：2013-12-19

Applicant: DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA

Inventor： Tomoo Morino ,  Shoji Mizuno ,  Yuichi Takeuchi ,  Akitaka Soeno ,  Yukihiko Watanabe

IPC: H01L29/16 ,  H01L29/78 ,  H01L29/10 ,  H01L27/088 ,  H01L29/12 ,  H01L21/761 ,  H01L29/06

Abstract: A silicon carbide semiconductor device includes: an element isolation layer and an electric field relaxation layer. The element isolation layer is arranged, from the surface of a base region to be deeper than the base region, between a main cell region and a sense cell region, and isolates the main cell region from the sense cell region. The electric field relaxation layer is arranged from a bottom of the base region to be deeper than the element isolation layer. The electric field relaxation layer is divided into a main cell region portion and a sense cell region portion. At least a part of the element isolation layer is arranged inside of a division portion of the electric field relaxation layer.

公开(公告)号：US10170470B2

公开(公告)日：2019-01-01

申请号：US15684057

申请日：2017-08-23

Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

Inventor： Toru Onishi ,  Katsuhiro Kutsuki ,  Yasushi Urakami ,  Yukihiko Watanabe

IPC: H01L29/78 ,  H01L29/06 ,  H01L27/088 ,  H01L29/423 ,  H01L29/16

Abstract: A switching device may include a semiconductor substrate; gate trenches; bottom insulating layers covering bottom surfaces of the gate trenches; gate insulating layers covering side surfaces of the gate trenches; and gate electrodes arranged in the gate trenches. The gate insulating layers in a center portion may have a first thickness and a first dielectric constant, and one or more of the gate insulating layers in a peripheral portion may have, within at least a part of the peripheral portion, a second thickness thicker than the first thickness and a second dielectric constant greater than the first dielectric constant. The semiconductor substrate may include a first region being in contact with the gate insulating layers, a body region being in contact with the gate insulating layers under the first region, and a second region being in contact with the gate insulating layers under the body region.

公开(公告)号：US12205983B2

公开(公告)日：2025-01-21

申请号：US17546248

申请日：2021-12-09

Applicant: DENSO CORPORATION

Inventor： Hidefumi Takaya ,  Yuichi Takeuchi ,  Yukihiko Watanabe

IPC: H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a semiconductor substrate having an element region and a terminal region located around the element region. The terminal region includes multiple guard rings and multiple first diffusion regions. When the semiconductor substrate is viewed in a plan view, one of the first diffusion regions is arranged correspondingly to one of the guard rings, and each of the guard rings is located in corresponding one of the first diffusion regions. A width of each of the first diffusion regions is larger than a width of corresponding one of the guard rings.

公开(公告)号：US10784335B2

公开(公告)日：2020-09-22

申请号：US16305164

申请日：2017-06-29

Applicant: DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA

Inventor： Yuichi Takeuchi ,  Shinichiro Miyahara ,  Atsuya Akiba ,  Katsumi Suzuki ,  Yukihiko Watanabe

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L29/872 ,  H01L29/47 ,  H01L29/12 ,  H01L21/04 ,  H01L29/739

Abstract: A top end of the p type connection layer is connected to the p type extension region. By forming such a p type extension region, it becomes possible to eliminate a region where an interval becomes large between the p type connection layer and the p type guard ring. Therefore, in the mesa portion, it is possible to prevent the equipotential line from excessively rising up, and it is possible to secure the withstand voltage.

公开(公告)号：US09818860B2

公开(公告)日：2017-11-14

申请号：US15365150

申请日：2016-11-30

Applicant: DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA ,  Masahiro Sugimoto ,  Hidefumi Takaya ,  Akitaka Soeno ,  Jun Morimoto

Inventor： Yuichi Takeuchi ,  Naohiro Suzuki ,  Masahiro Sugimoto ,  Hidefumi Takaya ,  Akitaka Soeno ,  Jun Morimoto ,  Narumasa Soejima ,  Yukihiko Watanabe

IPC: H01L29/78 ,  H01L29/16 ,  H01L21/82 ,  H01L29/417 ,  H01L29/66 ,  H01L29/10 ,  H01L29/872 ,  H01L21/04 ,  H01L21/306 ,  H01L21/308 ,  H01L29/423 ,  H01L21/761 ,  H01L29/15 ,  H01L29/06 ,  H01L29/08 ,  H01L29/861

CPC classification number: H01L29/7811 ,  H01L21/046 ,  H01L21/0475 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/761 ,  H01L21/8213 ,  H01L29/0615 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/157 ,  H01L29/158 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/861 ,  H01L29/872

Abstract: An SiC semiconductor device has a p type region including a low concentration region and a high concentration region filled in a trench formed in a cell region. A p type column is provided by the low concentration region, and a p+ type deep layer is provided by the high concentration region. Thus, since a SJ structure can be made by the p type column and the n type column provided by the n type drift layer, an on-state resistance can be reduced. As a drain potential can be blocked by the p+ type deep layer, at turnoff, an electric field applied to the gate insulation film can be alleviated and thus breakage of the gate insulation film can be restricted. Therefore, the SiC semiconductor device can realize the reduction of the on-state resistance and the restriction of breakage of the gate insulation film.

公开(公告)号：US20150129895A1

公开(公告)日：2015-05-14

申请号：US14402119

申请日：2013-06-06

Applicant: Kazumi CHIDA ,  DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA

Inventor： Yuichi Takeuchi ,  Kazumi Chida ,  Narumasa Soejima ,  Yukihiko Watanabe

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/78 ,  H01L21/04 ,  H01L29/16

CPC classification number: H01L29/66068 ,  H01L21/02529 ,  H01L21/0455 ,  H01L21/0475 ,  H01L21/049 ,  H01L21/3065 ,  H01L29/045 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7827

Abstract: In a method for producing an SiC semiconductor device, a p type layer is formed in a trench by epitaxially growing, and is then left only on a bottom portion and ends of the trench by hydrogen etching, thereby to form a p type SiC layer. Thus, the p type SiC layer can be formed without depending on diagonal ion implantation. Since it is not necessary to separately perform the diagonal ion implantation, it is less likely that a production process will be complicated due to transferring into an ion implantation apparatus, and thus manufacturing costs reduce. Since there is no damage due to a defect caused by the ion implantation, it is possible to reduce a drain leakage and to reliably restrict the p type SiC layer from remaining on the side surface of the trench.

Abstract translation: 在制造SiC半导体器件的方法中，通过外延生长在沟槽中形成p型层，然后仅通过氢蚀刻留在沟槽的底部和端部，从而形成p型SiC层。 因此，可以不依赖于对角离子注入来形成p型SiC层。 由于不需要单独进行对角线离子注入，因此生产工艺由于转移到离子注入装置中而不太可能复杂，因此制造成本降低。 由于由于离子注入引起的缺陷而没有损坏，因此可以减少漏极泄漏并且可靠地限制p型SiC层残留在沟槽的侧表面上。

公开(公告)号：US20150115286A1

公开(公告)日：2015-04-30

申请号：US14400365

申请日：2013-06-06

Applicant: Masahiro SUGIMOTO ,  Hidefumi TAKAYA ,  Akitaka SOENO ,  Jun MORIMOTO ,  DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA

Inventor： Yuichi Takeuchi ,  Naohiro Suzuki ,  Masahiro Sugimoto ,  Hidefumi Takaya ,  Akitaka Soeno ,  Jun Morimoto ,  Narumasa Soejima ,  Yukihiko Watanabe

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/308 ,  H01L29/10 ,  H01L21/04 ,  H01L21/306 ,  H01L29/66 ,  H01L29/16

CPC classification number: H01L29/7811 ,  H01L21/046 ,  H01L21/0475 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/761 ,  H01L21/8213 ,  H01L29/0615 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0661 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/157 ,  H01L29/158 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/861 ,  H01L29/872

Abstract: An SiC semiconductor device has a p type region including a low concentration region and a high concentration region filled in a trench formed in a cell region. A p type column is provided by the low concentration region, and a p+ type deep layer is provided by the high concentration region. Thus, since a SJ structure can be made by the p type column and the n type column provided by the n type drift layer, an on-state resistance can be reduced. As a drain potential can be blocked by the p+ type deep layer, at turnoff, an electric field applied to the gate insulation film can be alleviated and thus breakage of the gate insulation film can be restricted. Therefore, the SiC semiconductor device can realize the reduction of the on-state resistance and the restriction of breakage of the gate insulation film.

Abstract translation: SiC半导体器件具有包含低浓度区域和填充在形成于单元区域的沟槽中的高浓度区域的p型区域。 由低浓度区域提供p型列，并且由高浓度区域提供p +型深层。 因此，由于可以通过由n型漂移层提供的p型列和n型列来形成SJ结构，所以可以降低导通电阻。 由于漏极电位可以被p +型深层阻挡，所以在关断时，施加到栅极绝缘膜的电场可以减轻，从而可以限制栅极绝缘膜的破裂。 因此，SiC半导体器件可以实现导通电阻的降低和栅极绝缘膜的破损的限制。

公开(公告)号：US20150048382A1

公开(公告)日：2015-02-19

申请号：US14387425

申请日：2013-04-17

Applicant: DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA

Inventor： Yuichi Takeuchi ,  Kazumi Chida ,  Narumasa Soejima ,  Yukihiko Watanabe

IPC: H01L29/423 ,  H01L29/10 ,  H01L21/265 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/324 ,  H01L29/16 ,  H01L29/78

CPC classification number: H01L29/4236 ,  H01L21/044 ,  H01L21/0465 ,  H01L21/26513 ,  H01L21/3065 ,  H01L21/324 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/66734 ,  H01L29/7813

Abstract: In a silicon carbide semiconductor device, a p-type SiC layer is disposed in a corner of a bottom of a trench. Thus, even if an electric field is applied between a drain and a gate when a MOSFET is turned off, a depletion layer in a pn junction between the p-type SiC layer and an n− type drift layer greatly extends toward the n− type drift layer, and a high voltage caused by an influence of a drain voltage hardly enters a gate insulating film. Hence, an electric field concentration within the gate insulating film can be reduced, and the gate insulating film can be restricted from being broken. In this case, although the p-type SiC layer may be in a floating state, the p-type SiC layer is formed in only the corner of the bottom of the trench. Thus, the deterioration of the switching characteristic is relatively low.

Abstract translation: 在碳化硅半导体器件中，p型SiC层设置在沟槽底部的角部。 因此，即使当MOSFET截止时在漏极和栅极之间施加电场，p型SiC层和n型漂移层之间的pn结中的耗尽层大大向n型延伸 漂移层，并且由漏极电压的影响引起的高电压几乎不进入栅极绝缘膜。 因此，可以减小栅极绝缘膜内的电场集中，并且可以限制栅极绝缘膜破裂。 在这种情况下，虽然p型SiC层可以处于浮置状态，但是仅在沟槽底部的角部形成p型SiC层。 因此，开关特性的劣化相对较低。