公开(公告)号：US20100097087A1

公开(公告)日：2010-04-22

申请号：US12254397

申请日：2008-10-20

Applicant: John Hogeboom ,  Davide Tonietto

Inventor： John Hogeboom ,  Davide Tonietto

IPC: G01R31/3187

CPC classification number: G01R31/31711

Abstract: A built-in self test for receiver operation is provided through a testing method that evaluates characteristics of a received signal eye diagram. The receiver receives a serial data signal and applies compensation to that received serial data signal to generate a compensated serial data signal. The properties of an eye diagram associated with the compensated serial data signal are measured. In this context, certain desired eye diagram properties are characterized by parameters indicative of pass/fail criteria for receiver testing. The measured eye diagram properties are then compared against the parameters. A receiver testing conclusion signal is then output based on results of the comparison.

Abstract translation: 通过一种评估接收信号眼图特性的测试方法，提供内置的接收机操作自检。 接收器接收串行数据信号并对接收到的串行数据信号进行补偿以产生经补偿的串行数据信号。 测量与补偿的串行数据信号相关联的眼图的属性。 在这种情况下，某些所需的眼图属性的特征在于指示接收机测试的通过/不合格标准的参数。 然后将测量的眼图特性与参数进行比较。 然后根据比较结果输出接收机测试结论信号。

公开(公告)号：US20050135471A1

公开(公告)日：2005-06-23

申请号：US10823252

申请日：2004-04-13

Applicant: Davide Tonietto ,  Afshin Momtaz

Inventor： Davide Tonietto ,  Afshin Momtaz

IPC: H03L7/08 ,  H03L7/089 ,  H03L7/091 ,  H04L7/02 ,  H04L7/033 ,  H04L25/03 ,  H03K5/159

CPC classification number: H04L25/03057 ,  H03L7/0807 ,  H03L7/0891 ,  H03L7/091 ,  H04L7/0087 ,  H04L7/033 ,  H04L2025/0349

Abstract: In an integrated decision feedback equalizer and clock and data recovery circuit one or more flip-flops and/or latches may be shared. One or more flip-flops and/or latches may be used in retiming operations in a decision feedback equalizer and in phase detection operations in a clock recovery circuit. Outputs of the flip-flops and/or latches may be used to generate feedback signals for the decision feedback equalizer. The output of a flip-flop and/or latches may be used to generate signals that drive a charge pump in the clock recovery circuit.

Abstract translation: 在集成判决反馈均衡器和时钟和数据恢复电路中，可以共享一个或多个触发器和/或锁存器。 一个或多个触发器和/或锁存器可用于判决反馈均衡器中的重新定时操作以及时钟恢复电路中的相位检测操作。 可以使用触发器和/或锁存器的输出来产生用于判决反馈均衡器的反馈信号。 触发器和/或锁存器的输出可用于产生驱动时钟恢复电路中的电荷泵的信号。

公开(公告)号：US06351186B1

公开(公告)日：2002-02-26

申请号：US09564060

申请日：2000-05-03

Applicant: Paolo Cusinato ,  Gabriele Gandolfi ,  Vlttorio Colonna ,  Davide Tonietto

Inventor： Paolo Cusinato ,  Gabriele Gandolfi ,  Vlttorio Colonna ,  Davide Tonietto

IPC: H03F345

CPC classification number: H03F3/45273 ,  H03F3/3028 ,  H03F3/45264

Abstract: The invention relates to a Class AB operational amplifier providing both output gain enhancement and adaptative output bias. The operational amplifier includes first and second output terminals; a main differential stage having first and second differential inputs and a first differential output stage; a first adaptatively biased, boosted output stage coupling the first differential output stage to the output terminal. Each output stage includes a first NMOS output transistor having a control terminal, a first terminal coupled to the respective output terminal, and a second terminal, and includes a first output amplifier having a first input coupled to the second terminal of the first output transistor, a second input coupled to the first differential output stage to provide adaptative bias for the first boosted output stage, and an output coupled to the control terminal of the first output transistor.

Abstract translation: 本发明涉及一种提供输出增益增强和适应性输出偏置的AB类运算放大器。 运算放大器包括第一和第二输出端子; 主差分级具有第一和第二差分输入和第一差分输出级; 将第一差分输出级耦合到输出端的第一适应偏置的升压输出级。 每个输出级包括具有控制端的第一NMOS输出晶体管，耦合到相应的输出端的第一端和第二端，并且包括具有耦合到第一输出晶体管的第二端的第一输入的第一输出放大器， 耦合到所述第一差分输出级以提供所述第一升压输出级的适应偏置的第二输入以及耦合到所述第一输出晶体管的所述控制端的输出。

公开(公告)号：US10483343B2

公开(公告)日：2019-11-19

申请号：US15625731

申请日：2017-06-16

Applicant: Euhan Chong ,  Davide Tonietto ,  Zhonggui Xiang

Inventor： Euhan Chong ,  Davide Tonietto ,  Zhonggui Xiang

IPC: H01L49/02 ,  H01L23/00 ,  H04B5/00

Abstract: A device includes a first inductor positioned on a first substrate. The first inductor has at least one turn in a plane that is perpendicular to a plane of the first substrate. The first inductor is positioned for near field coupling with a second inductor. The second inductor is positioned on a second substrate, with at least one turn that is in a plane perpendicular to a plane of the second substrate. The second inductor is substantially parallel to the first inductor. Such an arrangement may be used for near field coupling, including edge-to-edge coupling, between two integrated circuits.

公开(公告)号：US09515785B2

公开(公告)日：2016-12-06

申请号：US14567068

申请日：2014-12-11

Applicant: Davide Tonietto ,  Henry Wong

Inventor： Davide Tonietto ,  Henry Wong

IPC: H04B3/46 ,  H04B17/00 ,  H04L1/20 ,  H04L27/01 ,  H04L7/00

CPC classification number: H04L1/20 ,  H04L7/0033 ,  H04L27/01

Abstract: Apparatus and methods are taught for quickly determining whether a Loss of Signal (LOS) condition has occurred for a receiver which includes an internal reference clock, a LOS circuit and a Clock and Data Recovery (CDR) circuit. The CDR circuit recovers the clock and data of an incoming signal. However, the LOS circuit can determine whether a received incoming signal includes an active signal, independent of said CDR circuit such that it samples said incoming signal utilizing said internal reference clock to determine a loss of signal prior to said CDR recovering the clock of said incoming signal. The LOS circuit includes an analog voltage threshold stage which samples the incoming signal, and produces at least one sample stream indicative of transitions in the incoming signal. The LOS circuit further includes a digital transition stage which counts transitions in order to discriminate between an active signal and noise.

Abstract translation: 教导了用于快速确定对于包括内部参考时钟，LOS电路和时钟和数据恢复（CDR）电路的接收机是否已经发生信号丢失（LOS）条件的装置和方法。 CDR电路恢复输入信号的时钟和数据。 然而，LOS电路可以确定接收到的输入信号是否包括有效信号，独立于所述CDR电路，使得其利用所述内部参考时钟采样所述输入信号，以在所述CDR恢复所述输入的时钟之前确定信号丢失 信号。 LOS电路包括模拟电压阈值级，其对输入信号进行采样，并产生指示输入信号中的转换的至少一个采样流。 LOS电路还包括数字转换级，其对转换进行计数，以便区分有效信号和噪声。

公开(公告)号：US20160173240A1

公开(公告)日：2016-06-16

申请号：US14567068

申请日：2014-12-11

Applicant: Davide Tonietto ,  Henry Wong

Inventor： Davide Tonietto ,  Henry Wong

IPC: H04L1/20 ,  H04L27/01 ,  H04L12/26

CPC classification number: H04L1/20 ,  H04L7/0033 ,  H04L27/01

Abstract: Apparatus and methods are taught for quickly determining whether a Loss of Signal (LOS) condition has occurred for a receiver which includes an internal reference clock, a LOS circuit and a Clock and Data Recovery (CDR) circuit. The CDR circuit recovers the clock and data of an incoming signal. However, the LOS circuit can determine whether a received incoming signal includes an active signal, independent of said CDR circuit such that it samples said incoming signal utilizing said internal reference clock to determine a loss of signal prior to said CDR recovering the clock of said incoming signal. The LOS circuit includes an analog voltage threshold stage which samples the incoming signal, and produces at least one sample stream indicative of transitions in the incoming signal. The LOS circuit further includes a digital transition stage which counts transitions in order to discriminate between an active signal and noise.

Abstract translation: 教导了用于快速确定对于包括内部参考时钟，LOS电路和时钟和数据恢复（CDR）电路的接收机是否已经发生信号丢失（LOS）条件的装置和方法。 CDR电路恢复输入信号的时钟和数据。 然而，LOS电路可以确定接收到的输入信号是否包括有效信号，独立于所述CDR电路，使得其利用所述内部参考时钟采样所述输入信号，以在所述CDR恢复所述输入的时钟之前确定信号丢失 信号。 LOS电路包括模拟电压阈值级，其对输入信号进行采样，并产生指示输入信号中的转换的至少一个采样流。 LOS电路还包括数字转换级，其对转换进行计数，以便区分有效信号和噪声。

公开(公告)号：US08228972B2

公开(公告)日：2012-07-24

申请号：US12132923

申请日：2008-06-04

Applicant: Davide Tonietto ,  John Hogeboom

Inventor： Davide Tonietto ,  John Hogeboom

IPC: H04B1/38

CPC classification number: H04L25/03343 ,  H04L1/205 ,  H04L1/243 ,  H04L2025/03356

Abstract: A first device transmits data over a first branch of a communications link toward a second device. That second device loops the received data pattern back over a second branch of the communications link. A bit error rate of the looped back data pattern is determined and a pre-emphasis applied to the transmitted data pattern is adjusted in response thereto. The first device further perturbs the data pattern communications signal so as to increase the bit error rate. The pre-emphasis is adjusted so as to reduce the determined bit error rate in the looped back data pattern in the presence of the perturbation. The steps for perturbing the signal and adjusting the pre-emphasis are iteratively performed, with the perturbation of the signal increasing with each iteration and adjustment of the pre-emphasis being refined with each iteration. The signal is perturbing by injecting modulation jitter into the signal (increasing each iteration) and adjusting amplitude of the signal (decreasing each iteration).

Abstract translation: 第一设备通过通信链路的第一分支向第二设备发送数据。 该第二设备将所接收的数据模式循环通过通信链路的第二分支。 确定环回数据模式的误码率，并响应于此来调整应用于发送数据模式的预加重。 第一设备进一步扰乱数据模式通信信号，以增加误码率。 调整预加重，以便在存在扰动的情况下减少确定的循环数据模式中的误码率。 迭代地执行用于干扰信号和调整预加重的步骤，随着每个迭代的信号的扰动增加，并且每次迭代改进预加重的调整。 该信号通过将调制抖动注入到信号（增加每次迭代）并调整信号的幅度（每次迭代减少）来扰乱。

公开(公告)号：US07317769B2

公开(公告)日：2008-01-08

申请号：US10418009

申请日：2003-04-17

Applicant: Davide Tonietto ,  Ali Ghiasi

Inventor： Davide Tonietto ,  Ali Ghiasi

IPC: H03D1/00

CPC classification number: G11B20/10027 ,  G11B20/10009 ,  G11B20/10046 ,  G11B20/10222 ,  H04J3/04 ,  H04J3/0685 ,  H04L1/205 ,  H04L25/03159 ,  H04L25/03343 ,  H04L25/03885 ,  H04L25/20 ,  H04L2025/03401

Abstract: A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a Printed Circuit Board (PCB). The high-speed bit stream interface includes a line side interface, a board side interface, and a signal conditioning circuit. The signal conditioning circuit services each of an RX path and a TX path and includes a limiting amplifier and a clock and data recovery circuit. The signal conditioning circuit may also include an equalizer and/or an output pre-emphasis circuit. The limiting amplifier applies respective gains to the RX path and to the TX path that are based upon respective dynamic ranges of the incoming signals.

Abstract translation: 高速位流接口模块通过印刷电路板（PCB）将高速通信介质与通信专用集成电路（ASIC）接口。 高速比特流接口包括线路侧接口，电路板侧接口和信号调理电路。 信号调理电路为RX路径和TX路径提供服务，并且包括限幅放大器和时钟和数据恢复电路。 信号调理电路还可以包括均衡器和/或输出预加重电路。 限幅放大器根据输入信号的相应动态范围，将相应的增益应用于RX路径和TX路径。

公开(公告)号：US10009035B1

公开(公告)日：2018-06-26

申请号：US15495572

申请日：2017-04-24

Applicant: Marc-Andre LaCroix ,  Semyon Lebedev ,  Henry Wong ,  Davide Tonietto

Inventor： Marc-Andre LaCroix ,  Semyon Lebedev ,  Henry Wong ,  Davide Tonietto

IPC: H03M1/06 ,  H03M1/08 ,  H04B1/38 ,  H03M1/12 ,  H04L25/06 ,  H03M1/00

CPC classification number: H04B1/38 ,  H03M1/00 ,  H03M1/007 ,  H03M1/12 ,  H03M1/1215 ,  H03M1/46 ,  H04L25/067

Abstract: Methods, systems and devices for dynamically controlling resolution of an analog-to-digital converter (ADC). The ADC receives an analog input signal and outputs digital data. A statistical unit coupled to the ADC obtains samples of the output signal and transmits a control signal to the ADC to adjust the resolution of the ADC. The control signal is generated by the statistical unit based on a comparison of at least one performance indicator with a target performance level. The at least one performance indicator is calculated using the samples.

公开(公告)号：US07664170B2

公开(公告)日：2010-02-16

申请号：US10417990

申请日：2003-04-17

Applicant: Davide Tonietto ,  Ali Ghiasi

Inventor： Davide Tonietto ,  Ali Ghiasi

IPC: H03H7/30

CPC classification number: G11B20/10027 ,  G11B20/10009 ,  G11B20/10046 ,  H04J3/04 ,  H04L1/205 ,  H04L25/03343 ,  H04L25/03885

Abstract: A high-speed bit stream interface module interfaces a high-speed communication media to a communication Application Specific Integrated Circuit (ASIC) via a Printed Circuit Board (PCB). The high-speed bit stream interface includes a line side interface, a board side interface, and a signal conditioning circuit. The signal conditioning circuit services each of an RX path and a TX path and includes a limiting amplifier and a clock and data recovery circuit. The signal conditioning circuit includes an AGC loop, an equalizer, and an equalizer feedback loop. The AGC loop includes a gain path and a feedback path that couples to the output of the equalizer. The equalizer feedback loop couples to the output of the equalizer and produces spectral shaping control settings that the equalizer uses to produce an equalized high-speed serial bit stream at an equalizer output.

Abstract translation: 高速位流接口模块通过印刷电路板（PCB）将高速通信介质与通信专用集成电路（ASIC）接口。 高速比特流接口包括线路侧接口，电路板侧接口和信号调理电路。 信号调理电路为RX路径和TX路径提供服务，并且包括限幅放大器和时钟和数据恢复电路。 信号调理电路包括AGC环路，均衡器和均衡器反馈环路。 AGC环路包括增益路径和耦合到均衡器的输出的反馈路径。 均衡器反馈环路耦合到均衡器的输出，并产生频谱整形控制设置，均衡器用于在均衡器输出端产生均衡的高速串行比特流。