Synchronous communication between execution environments in a data
processing system employing an object-oriented memory protection
mechanism
    14.
    发明授权
    Synchronous communication between execution environments in a data processing system employing an object-oriented memory protection mechanism 失效
    在采用面向对象的存储器保护机制的数据处理系统中的执行环境之间的同步通信

    公开(公告)号:US5157777A

    公开(公告)日:1992-10-20

    申请号:US729869

    申请日:1991-07-11

    IPC分类号: G06F9/40 G06F9/46

    CPC分类号: G06F9/468 G06F9/4425

    摘要: A subsystem call mechanism for communicating between a first execution environment associated with a first domain object, and a second execution environment associated with a second domain object. An environment table object is associated with a process object. The environment table object includes a control stack which is an array of control stack entries which entries save the state of the first calling execution environment to be restored on a return from the second execution environment. A subsystem entry in the subsystem table specifies the object that defines region 2 of the target execution environment and the frame pointer of the topmost stack frame in the target environment, a supervisor Stack Pointer that is a linear address for the supervisor stack used when involving a supervisor call in the user mode (instead of the stack pointer in the current frame) to locate the new frame. The first domain object further includes Procedure Entries that specify the type and address of the target procedure. Each of the procedure entries includes a Procedure Entry Type field that indicates the type of procedure to be invoked, either a supervisor procedure or a subsystem procedure, and an offset into the target execution environment. The offset specifies the first instruction of the target procedure.

    摘要翻译: 用于在与第一域对象相关联的第一执行环境和与第二域对象相关联的第二执行环境之间进行通信的子系统调用机制。 环境表对象与进程对象相关联。 环境表对象包括控制堆栈,它是控制堆栈条目的数组,条目保存要从第二执行环境的返回恢复的第一调用执行环境的状态。 子系统表中的子项目指定了定义目标执行环境的区域2和目标环境中最上层堆栈帧的帧指针的对象,作为涉及到的主管栈的线程地址的管理程序堆栈指针 主管调用用户模式(而不是当前帧中的堆栈指针)来定位新帧。 第一个域对象还包括指定目标过程的类型和地址的过程条目。 每个过程条目包括一个过程条目类型字段,指示要调用的过程的类型,主管过程或子系统过程,以及到目标执行环境的偏移量。 偏移量指定目标过程的第一条指令。

    DEBUGGING PARALLEL SOFTWARE USING SPECULATIVELY EXECUTED CODE SEQUENCES IN A MULTIPLE CORE ENVIRONMENT
    18.
    发明申请
    DEBUGGING PARALLEL SOFTWARE USING SPECULATIVELY EXECUTED CODE SEQUENCES IN A MULTIPLE CORE ENVIRONMENT 有权
    在多个核心环境中使用规范执行的代码序列调试并行软件

    公开(公告)号:US20110197182A1

    公开(公告)日:2011-08-11

    申请号:US12978480

    申请日:2010-12-24

    IPC分类号: G06F9/44

    摘要: Methods and apparatus relating to debugging parallel software using speculatively executed code sequences in a multiple core environment are described. In an embodiment, occurrence of a speculative code debug event is detected and a speculative code execution debug module is executed in response to occurrence of the event. Other embodiments are also disclosed and claimed.

    摘要翻译: 描述了在多核心环境中使用推测执行的代码序列调试并行软件的方法和装置。 在一个实施例中,检测到推测代码调试事件的发生,并且响应于事件的发生而执行推测代码执行调试模块。 还公开并要求保护其他实施例。

    Apparatus and method for caching lock conditions in a multi-processor
system
    19.
    发明授权
    Apparatus and method for caching lock conditions in a multi-processor system 失效
    用于在多处理器系统中缓存锁定条件的装置和方法

    公开(公告)号:US6006299A

    公开(公告)日:1999-12-21

    申请号:US204592

    申请日:1994-03-01

    IPC分类号: G06F9/46 G06F13/08

    CPC分类号: G06F9/52

    摘要: In a computer system, an apparatus for handling lock conditions wherein a first instruction executed by a first processor processes data that is common to a second processor while the second processor is locked from simultaneously executing a second instruction that also processes this same data. A lock bit is set when the first processor begins execution of the first instruction. Thereupon, the second processor is prevented from executing its instruction until the first processor has completed its processing of the shared data. Hence, the second processor queues its request in a buffer. The lock bit is cleared after the first processor has completed execution of its instruction. The first processor then checks the buffer for any outstanding requests. In response to the second processor's queued request, the first processor transmits a signal to the second processor indicating that the data is now not locked.

    摘要翻译: 在计算机系统中,一种用于处理锁定条件的装置,其中由第一处理器执行的第一指令在第二处理器被锁定时处理与第二处理器相同的数据,同时执行也处理该相同数据的第二指令。 当第一个处理器开始执行第一个指令时,锁定位被置位。 于是,第二处理器被阻止执行其指令,直到第一处理器完成对共享数据的处理。 因此,第二处理器将其请求排队在缓冲器中。 在第一个处理器完成其指令执行后,锁定位被清零。 然后,第一个处理器检查缓冲区是否有任何未完成的请求。 响应于第二处理器的排队请求,第一处理器向第二处理器发送指示数据现在不被锁定的信号。

    Apparatus for maintaining multilevel cache hierarchy coherency in a
multiprocessor computer system
    20.
    发明授权
    Apparatus for maintaining multilevel cache hierarchy coherency in a multiprocessor computer system 失效
    用于在多处理器计算机系统中维持多级高速缓存层级一致性的装置

    公开(公告)号:US5715428A

    公开(公告)日:1998-02-03

    申请号:US639719

    申请日:1996-04-29

    IPC分类号: G06F12/08 G06F13/00

    CPC分类号: G06F12/0831 G06F12/0811

    摘要: A computer system comprising a plurality of caching agents with a cache hierarchy, the caching agents sharing memory across a system bus and issuing memory access requests in accordance with a protocol wherein a line of a cache has a present state comprising one of a plurality of line states. The plurality of line states includes a modified (M) state, wherein a line of a first caching agent in M state has data which is more recent than any other copy in the system; an exclusive (E) state, wherein a line in E state in a first caching agent is the only one of the agents in the system which has a copy of the data in a line of the cache, the first caching agent modifying the data in the cache line independent of other said agents coupled to the system bus; a shared (S) state, wherein a line in S state indicates that more than one of the agents has a copy of the data in the line; and an invalid (I) state indicating that the line does not exist in the cache. A read or a write to a line in I state results in a cache miss. The present invention associates states with lines and defines rules governing state transitions. State transitions depend on both processor generated activities and activities by other bus agents, including other processors. Data consistency is guaranteed in systems having multiple levels of cache and shared memory and/or multiple active agents, such that no agent ever reads stale data and actions are serialized as needed.

    摘要翻译: 一种计算机系统,包括具有高速缓存层级的多个高速缓存代理,所述高速缓存代理器通过系统总线共享存储器并根据协议发出存储器访问请求,其中高速缓存行具有包括多条线路之一的当前状态 状态。 多个行状态包括修改的(M)状态,其中M状态的第一高速缓存代理的行具有比系统中的任何其他副本更新的数据; 排除(E)状态,其中第一高速缓存代理中的E状态中的线是系统中唯一具有高速缓存行中的数据的副本的代理,第一高速缓存代理将数据修改为 所述高速缓存行独立于耦合到所述系统总线的其它所述代理; 共享(S)状态,其中S状态的行指示多于一个代理具有该行中的数据的副本; 和指示该行不存在于缓存中的无效(I)状态。 对I状态的行进行读取或写入会导致高速缓存未命中。 本发明将状态与线相关联并且定义了管理状态转换的规则。 状态转换取决于处理器生成的活动和其他总线代理(包括其他处理器)的活动。 在具有多级缓存和共享内存和/或多个活动代理的系统中保证数据一致性,使得任何代理程序都不会读取过时的数据,并且操作根据需要进行序列化。