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21 条记录 (耗时 0.019 秒)

    Selective switching of a transistor's back gate potential
    11.
    发明授权
    Selective switching of a transistor's back gate potential 失效
    选择性切换晶体管的背栅电位

    公开(公告)号：US06985023B2

    公开(公告)日：2006-01-10

    申请号：US10768394

    申请日：2004-01-30

    申请人： Mami Kawabata ,  Masahiro Yoshihara ,  Eiichi Makino

    发明人： Mami Kawabata ,  Masahiro Yoshihara ,  Eiichi Makino

    IPC分类号： H03K19/0185 ,  H03K17/687

    CPC分类号： G05F1/56 ,  G11C5/147 ,  H01L27/105

    摘要： A semiconductor device comprises a first transistor and a potential generator circuit. The first transistor has a first conduction type first semiconductor region and a second conduction type second semiconductor region formed in the first semiconductor region. The first and second semiconductor regions are supplied with first and second prescribed potentials, respectively. The potential generator circuit generates the first prescribed potential. The potential generator circuit has a first power supply terminal supplied with a first power supply potential, a second power supply terminal supplied with a second power supply potential set to a higher potential than the first power supply potential, and an output terminal outputting the first prescribed potential. The potential generator circuit outputs the second power supply potential when the second power supply potential is higher than a predetermined potential, and the first power supply potential when the second power supply potential is lower than the predetermined potential.

    摘要翻译： 半导体器件包括第一晶体管和电位发生器电路。 第一晶体管具有形成在第一半导体区域中的第一导电型第一半导体区域和第二导电型第二半导体区域。 第一和第二半导体区域分别被提供第一和第二规定电位。 电位发生器电路产生第一规定电位。 电位发生器电路具有被提供有第一电源电位的第一电源端子，被提供有设置为比第一电源电位高的电位的第二电源电位的第二电源端子以及输出第一规定 潜在。 当第二电源电位高于预定电位时，电位发生器电路输出第二电源电位，而当第二电源电位低于预定电位时，该第一电源电位。

    Semiconductor integrated circuit device
    12.
    发明授权
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US08325532B2

    公开(公告)日：2012-12-04

    申请号：US12754149

    申请日：2010-04-05

    申请人： Eiichi Makino

    发明人： Eiichi Makino

    IPC分类号： G11C16/02 ,  G11C5/14 ,  G11C8/00 ,  G11C11/00

    CPC分类号： G11C16/30 ,  G11C5/145

    摘要： A semiconductor integrated circuit device includes a memory cell array including a plurality of planes each including a plurality of memory cells, a power supply voltage generating circuit including a voltage generating circuit configured to generate a power supply voltage common to the plurality of planes, a select number detection circuit configured to detect a number of selected planes of the plurality of planes, and a resistance variable circuit configured to vary a wiring resistance between the plurality of planes and the voltage generating circuit in accordance with the number of selected planes, which is reported from the select number detection circuit, and a control circuit configured to control the power supply voltage generating circuit.

    摘要翻译： 一种半导体集成电路装置，具备包括多个存储单元的多个平面的存储单元阵列，电源电压生成电路，具备：电压生成电路，其被配置为生成上述多个面共有的电源电压;选择部 数字检测电路，被配置为检测所述多个平面中的选定平面的数量;以及电阻可变电路，被配置为根据所选择的平面的数量来改变所述多个平面与所述电压产生电路之间的布线电阻 以及被配置为控制电源电压产生电路的控制电路。

    Systems and methods for wiring circuit components
    13.
    发明授权
    Systems and methods for wiring circuit components 失效
    接线电路组件的系统和方法

    公开(公告)号：US07219323B2

    公开(公告)日：2007-05-15

    申请号：US11107038

    申请日：2005-04-15

    申请人： Eiichi Makino

    发明人： Eiichi Makino

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： Systems and methods for arranging parallel wires to reduce the capacitance variations. In one embodiment, multiple first components arranged as a linear array are coupled to a second component at the end of this linear array by corresponding signal wires. Each signal wire has a perpendicular portion extending perpendicular to the direction of the linear array, and a parallel portion which runs parallel to the direction of the linear array. The parallel portions are staggered so that longer ones of the parallel portions are adjacent to the shorter ones of the parallel portions, instead of simply being arranged from longest to shortest. In one embodiment, the longer half of the parallel portions decrease in length across the series of parallel portions, while the shorter half of the parallel portions increase in length. In another embodiment, successively longer/shorter parallel portions alternate sides of the series.

    摘要翻译： 用于布置平行导线以减小电容变化的系统和方法。 在一个实施例中，布置成线性阵列的多个第一部件通过对应的信号线耦合到该线性阵列的末端处的第二部件。 每个信号线具有垂直于线性阵列方向延伸的垂直部分，以及平行于线性阵列方向延伸的平行部分。 平行部分交错，使得更长的平行部分与较短的平行部分相邻，而不是简单地从最长到最短的布置。 在一个实施例中，平行部分的较长的一半在整个平行部分的长度上减小，而平行部分的较短的一半长度增加。 在另一个实施例中，连续更长/更短的平行部分是该系列的交替侧。

    Semiconductor memory device of shared sense amplifier system
    14.
    发明授权
    Semiconductor memory device of shared sense amplifier system 有权
    共享读出放大器系统的半导体存储器件

    公开(公告)号：US06343038B1

    公开(公告)日：2002-01-29

    申请号：US09653264

    申请日：2000-08-31

    申请人： Eiichi Makino ,  Yohji Watanabe ,  Daisuke Kato

    发明人： Eiichi Makino ,  Yohji Watanabe ,  Daisuke Kato

    IPC分类号： G11C700

    CPC分类号： G11C7/12 ,  G11C11/4094 ,  G11C29/14

    摘要： In a semiconductor memory device including a bit line precharge/equalizing circuit, the control system of the bit line precharge/equalizing circuit is changed in the normal operation mode and in the test mode. In the test mode, the bit line precharge/equalizing circuit is temporarily turned ON when an internal activation signal becomes non-active and then the bit line precharge/equalizing circuit is turned OFF after the potentials of paired bit lines are completely equalized.

    摘要翻译： 在包括位线预充电/均衡电路的半导体存储器件中，位线预充电/均衡电路的控制系统在正常工作模式和测试模式下改变。 在测试模式下，当内部激活信号变为非有效时，位线预充电/均衡电路暂时导通，然后位线预充电/均衡电路在配对位线的电位完全相等之后变为截止。

    Apparatus and method for controlling table in medical diagnosis system
    15.
    发明授权
    Apparatus and method for controlling table in medical diagnosis system 失效
    医疗诊断系统中表格的设备及方法

    公开(公告)号：US6045262A

    公开(公告)日：2000-04-04

    申请号：US44226

    申请日：1998-03-19

    申请人： Yoshikazu Igeta ,  Eiichi Makino ,  Mikio Mochitate ,  Hiroshi Abe ,  Takeshi Yano

    发明人： Yoshikazu Igeta ,  Eiichi Makino ,  Mikio Mochitate ,  Hiroshi Abe ,  Takeshi Yano

    IPC分类号： A61B5/055 ,  A61B6/04

    CPC分类号： A61B6/0457 ,  A61B6/548

    摘要： A control apparatus for controlling movement of a table supporting an object under inspection in a medical diagnosis system includes a driving power unit for moving the table, a position detector for outputting a signal indicating a position of the table, a positioning servo-control unit for controlling the driving power unit so that the detected position signal coincides with a given desired value, a manipulating force detector for outputting a force signal corresponding to a manipulating force applied by an operator, a force-to-position conversion unit for converting the force signal into a position change quantity for the table, a force control unit for controlling the driving power unit in accordance with the position change quantity so long as the manipulating force is being detected, and a change-over unit for selecting either the positioning servo-control unit or the force control unit in response to operation of the operator.

    摘要翻译： 一种用于控制在医疗诊断系统中支撑检查对象的台的移动的控制装置，包括：用于移动工作台的驱动力单元，用于输出表示工作台位置的信号的位置检测器;定位伺服控制单元， 控制所述驱动功率单元，使得所检测的位置信号与给定的期望值一致;操作力检测器，用于输出对应于由操作者施加的操纵力的力信号;力到位置转换单元，用于将所述力信号 进入台的位置变化量;只要检测到操作力，根据位置变化量控制驱动力单元的力控制单元，以及用于选择定位伺服控制 单元或力控制单元响应于操作者的操作。

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF ARRANGING WIRINGS IN THE SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    17.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD OF ARRANGING WIRINGS IN THE SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
    半导体集成电路装置及其在半导体集成电路装置中布线的方法

    公开(公告)号：US20090261386A1

    公开(公告)日：2009-10-22

    申请号：US12426444

    申请日：2009-04-20

    申请人： Eiichi Makino

    发明人： Eiichi Makino

    IPC分类号： H01L29/00 ,  H01L21/82

    CPC分类号： H01L27/101 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/24

    摘要： A semiconductor integrated circuit device includes a first component, a second component, a plurality of first, second and third contacts, and a plurality of signal lines having a plurality of first wires, and connecting the first and second component, each of the first wires having a first, second, third and fourth part, each of the parts having a resistivity, the second part having a first resistivity, a different value of the first resistance being set for each of the plurality of first wires, the first, third and fourth parts having a second or third resistivity which is lower than the first resistivity, the first and second part being electrically connected in series by the first contact, the second and third part being electrically connected in series by the second contact, and the third and fourth part being electrically connected in series by the third contact.

    摘要翻译： 半导体集成电路器件包括第一元件，第二元件，多个第一，第二和第三触点，以及多个具有多个第一布线的信号线，并且连接第一和第二元件，每个第一布线 具有第一，第二，第三和第四部分，每个部分具有电阻率，第二部分具有第一电阻率，为多个第一电线中的每一个设置第一电阻的不同值，第一，第三和第 第四部分具有低于第一电阻率的第二或第三电阻率，第一和第二部分通过第一接触串联电连接，第二和第三部分由第二接触串联电连接，第三部分和第三部分 第四部分通过第三触点串联电连接。

    SEMICONDUCTOR DEVICE, RELAY CHIP, AND METHOD FOR PRODUCING RELAY CHIP
    18.
    发明申请
    SEMICONDUCTOR DEVICE, RELAY CHIP, AND METHOD FOR PRODUCING RELAY CHIP 失效
    半导体器件，继电器芯片和生产继电器芯片的方法

    公开(公告)号：US20080054491A1

    公开(公告)日：2008-03-06

    申请号：US11851118

    申请日：2007-09-06

    申请人： Eiichi Makino ,  Shigeo Ohshima ,  Naohisa Okumura

    发明人： Eiichi Makino ,  Shigeo Ohshima ,  Naohisa Okumura

    IPC分类号： H01L23/50 ,  H05K1/00 ,  H05K3/10

    CPC分类号： H01L23/5385 ,  H01L23/13 ,  H01L23/5386 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0652 ,  H01L25/18 ,  H01L2223/5448 ,  H01L2224/05554 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49433 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/30105 ,  Y10T29/49162 ,  H01L2924/00014 ,  H01L2924/00

    摘要： A semiconductor device according to the present invention includes a substrate including a plurality of first pads thereon; at least one semiconductor chip including a plurality of second pads; and at least one wiring chip including a plurality of third pads. A part of the plurality of second pads of the semiconductor chip is electrically connected to a part of the plurality of third pads of the wiring chip, and another part of the plurality of third pads of the wiring chip is electrically connected to a part of the plurality of first pads of the substrate. The plurality of third pads of the wiring chip are located along two adjacent sides of a wiring chip substrate of the wiring chip, and are connected to each other by a plurality of metal wires, sequentially from the third pads closest from a contact point of the two sides; The plurality of metal wires each include a first part drawn from each of the plurality of third pads located along a first side of the two sides inward the wiring chip so as to be parallel to, or so as to form an acute angle with, a second side of the two sides, a second part drawn from each of the plurality of third pads located along the second side inward the wiring chip so as to be parallel to, or so as to form an acute angle with, the first side, and a third part connecting the first part and the second part to each other in a straight manner. The plurality of metal wires are formed such that a wiring width of each metal wire, a wiring interval between each metal wire and a metal wire adjacent and outer thereto, and a wiring pitch which is a sum of each wiring width and a corresponding wiring interval are set so as to minimize a difference between wiring capacitances of each adjacent metal wires among the plurality of metal wires.

    摘要翻译： 根据本发明的半导体器件包括其上包括多个第一焊盘的衬底; 至少一个半导体芯片，包括多个第二焊盘; 以及包括多个第三焊盘的至少一个布线芯片。 半导体芯片的多个第二焊盘的一部分电连接到布线芯片的多个第三焊盘的一部分，并且布线芯片的多个第三焊盘的另一部分电连接到 多个基片的第一垫片。 布线芯片的多个第三焊盘沿着布线芯片的布线芯片基板的两个相邻侧布置，并且从多个金属布线彼此连接，从最接近 双方; 多个金属线各自包括从沿着两侧的第一侧向内布置的多个第三焊盘中的每一个的第一部分，其与平行于或与之形成锐角的第一部分 所述两侧的第二侧，从所述多个第三焊盘中的每一个沿着所述第二侧向内布置在所述布线芯片上的第二部分，以与所述第一侧平行或与之形成锐角;以及 将第一部分和第二部分以直线方式彼此连接的第三部分。 多个金属线被形成为使得每个金属线的布线宽度，每个金属布线和与其外部的金属线之间的布线间隔以及布线间距是每个布线宽度和相应的布线间隔之和的布线间距 被设置为使多个金属线中的每个相邻的金属线的布线电容之间的差最小化。

    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
    19.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 审中-公开
    非易失性半导体存储器件

    公开(公告)号：US20070206419A1

    公开(公告)日：2007-09-06

    申请号：US11682564

    申请日：2007-03-06

    申请人： Eiichi Makino

    发明人： Eiichi Makino

    IPC分类号： G11C5/02 ,  G11C16/04 ,  G11C5/06 ,  G11C11/34

    CPC分类号： G11C5/025 ,  G11C5/063

    摘要： A nonvolatile semiconductor memory device having a first memory cell array including a plurality of electrically reprogrammable and erasable nonvolatile memory cells formed in a first area of a semiconductor substrate, a second memory cell array including a plurality of electrically reprogrammable and erasable nonvolatile memory cells formed in second area different from said first area of said semiconductor substrate, said first and second memory cell arrays being arranged in a first direction, a first page buffer block for storing data from said first memory cell array, said first page buffer block being arranged in said first memory cell array along a first direction, a second page buffer block for storing data from said second memory cell array, said second page buffer block being arranged in said second memory cell array along said first direction, a pad section for inputting data to and outputting data from said first memory cell array and said second memory cell array, said pad section having a plurality of pads arranged in an end of a semiconductor chip along a second direction perpendicular to said first direction, a first data line for supplying data from said first memory cell array to said pad section, said first data line being arranged in said first memory cell array along said first direction and a second data line for supplying data from said second memory cell array to said pad section, said second data line being arranged in said second memory cell array along said first direction over said first page buffer block.

    摘要翻译： 一种具有第一存储单元阵列的非易失性半导体存储器件，所述第一存储单元阵列包括形成在半导体衬底的第一区域中的多个电可重新编程和可擦除非易失性存储单元，第二存储单元阵列包括多个电可重新编程和可擦除非易失性存储单元， 第二区域与所述半导体衬底的所述第一区域不同，所述第一和第二存储单元阵列沿第一方向布置，第一页缓冲块，用于存储来自所述第一存储单元阵列的数据，所述第一页缓冲块布置在所述第一存储单元阵列中 沿着第一方向的第一存储单元阵列，用于存储来自所述第二存储单元阵列的数据的第二页缓冲块，所述第二页缓冲块沿着所述第一方向布置在所述第二存储单元阵列中，用于将数据输入到 从所述第一存储单元阵列和所述第二存储单元阵列输出数据 具有沿垂直于所述第一方向的第二方向布置在半导体芯片的端部的多个焊盘的第一数据线，用于将数据从所述第一存储单元阵列提供给所述焊盘部分的第一数据线，所述第一数据线布置在所述 第一存储单元阵列沿着所述第一方向和第二数据线，用于将数据从所述第二存储单元阵列提供给所述焊盘部分，所述第二数据线沿着所述第一方向在所述第一页缓冲块上布置在所述第二存储单元阵列中。

    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
    20.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 审中-公开
    非易失性半导体存储器件

    公开(公告)号：US20070206399A1

    公开(公告)日：2007-09-06

    申请号：US11682478

    申请日：2007-03-06

    申请人： Eiichi Makino ,  Koji Hosono ,  Kazushige Kanda ,  Shigeo Ohshima

    发明人： Eiichi Makino ,  Koji Hosono ,  Kazushige Kanda ,  Shigeo Ohshima

    IPC分类号： G11C5/02 ,  G11C5/06

    CPC分类号： G11C5/025 ,  G11C5/063 ,  G11C16/0483 ,  H01L2224/06155 ,  H01L2224/06156 ,  H01L2224/48227 ,  H01L2924/15311

    摘要： A nonvolatile semiconductor memory device having a first memory cell array including a plurality of electrical reprogramming and erasable nonvolatile semiconductor memory cells formed in a first area of a semiconductor substrate, a second memory cell array including a plurality of electrical reprogramming and erasable nonvolatile semiconductor memory cells formed in a second area different from said first area of said semiconductor substrate, said first and second memory cell arrays being arranged in a first direction, and a first pad section for inputting data to and outputting data from said first memory cell array and said second memory cell array, said first pad section having a plurality of pads arranged between said first memory cell array and said second memory cell array along a second direction perpendicular to said first direction.

    摘要翻译： 一种具有第一存储单元阵列的非易失性半导体存储器件，包括形成在半导体衬底的第一区域中的多个电重新编程和可擦除非易失性半导体存储单元，第二存储单元阵列包括多个电重编程和可擦除非易失性半导体存储单元 形成在与所述半导体衬底的所述第一区域不同的第二区域中，所述第一和第二存储单元阵列沿第一方向布置;以及第一焊盘区段，用于向所述第一存储单元阵列和所述第二存储单元阵列输入数据并输出数据 所述第一焊盘部分具有沿垂直于所述第一方向的第二方向布置在所述第一存储单元阵列和所述第二存储单元阵列之间的多个焊盘。