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    SEMICONDUCTOR DEVICE, RELAY CHIP, AND METHOD FOR PRODUCING RELAY CHIP
    2.
    发明申请
    SEMICONDUCTOR DEVICE, RELAY CHIP, AND METHOD FOR PRODUCING RELAY CHIP 失效
    半导体器件，继电器芯片和生产继电器芯片的方法

    公开(公告)号：US20080054491A1

    公开(公告)日：2008-03-06

    申请号：US11851118

    申请日：2007-09-06

    申请人： Eiichi Makino ,  Shigeo Ohshima ,  Naohisa Okumura

    发明人： Eiichi Makino ,  Shigeo Ohshima ,  Naohisa Okumura

    IPC分类号： H01L23/50 ,  H05K1/00 ,  H05K3/10

    CPC分类号： H01L23/5385 ,  H01L23/13 ,  H01L23/5386 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0652 ,  H01L25/18 ,  H01L2223/5448 ,  H01L2224/05554 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45155 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49433 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01021 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/30105 ,  Y10T29/49162 ,  H01L2924/00014 ,  H01L2924/00

    摘要： A semiconductor device according to the present invention includes a substrate including a plurality of first pads thereon; at least one semiconductor chip including a plurality of second pads; and at least one wiring chip including a plurality of third pads. A part of the plurality of second pads of the semiconductor chip is electrically connected to a part of the plurality of third pads of the wiring chip, and another part of the plurality of third pads of the wiring chip is electrically connected to a part of the plurality of first pads of the substrate. The plurality of third pads of the wiring chip are located along two adjacent sides of a wiring chip substrate of the wiring chip, and are connected to each other by a plurality of metal wires, sequentially from the third pads closest from a contact point of the two sides; The plurality of metal wires each include a first part drawn from each of the plurality of third pads located along a first side of the two sides inward the wiring chip so as to be parallel to, or so as to form an acute angle with, a second side of the two sides, a second part drawn from each of the plurality of third pads located along the second side inward the wiring chip so as to be parallel to, or so as to form an acute angle with, the first side, and a third part connecting the first part and the second part to each other in a straight manner. The plurality of metal wires are formed such that a wiring width of each metal wire, a wiring interval between each metal wire and a metal wire adjacent and outer thereto, and a wiring pitch which is a sum of each wiring width and a corresponding wiring interval are set so as to minimize a difference between wiring capacitances of each adjacent metal wires among the plurality of metal wires.

    摘要翻译： 根据本发明的半导体器件包括其上包括多个第一焊盘的衬底; 至少一个半导体芯片，包括多个第二焊盘; 以及包括多个第三焊盘的至少一个布线芯片。 半导体芯片的多个第二焊盘的一部分电连接到布线芯片的多个第三焊盘的一部分，并且布线芯片的多个第三焊盘的另一部分电连接到 多个基片的第一垫片。 布线芯片的多个第三焊盘沿着布线芯片的布线芯片基板的两个相邻侧布置，并且从多个金属布线彼此连接，从最接近 双方; 多个金属线各自包括从沿着两侧的第一侧向内布置的多个第三焊盘中的每一个的第一部分，其与平行于或与之形成锐角的第一部分 所述两侧的第二侧，从所述多个第三焊盘中的每一个沿着所述第二侧向内布置在所述布线芯片上的第二部分，以与所述第一侧平行或与之形成锐角;以及 将第一部分和第二部分以直线方式彼此连接的第三部分。 多个金属线被形成为使得每个金属线的布线宽度，每个金属布线和与其外部的金属线之间的布线间隔以及布线间距是每个布线宽度和相应的布线间隔之和的布线间距 被设置为使多个金属线中的每个相邻的金属线的布线电容之间的差最小化。

    Semiconductor integrated circuit device
    3.
    发明授权
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号：US07602651B2

    公开(公告)日：2009-10-13

    申请号：US11953319

    申请日：2007-12-10

    申请人： Eiichi Makino ,  Shigeo Ohshima

    发明人： Eiichi Makino ,  Shigeo Ohshima

    IPC分类号： G11C16/06

    CPC分类号： G11C16/26 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1063 ,  G11C2207/105

    摘要： This disclosure concerns a device outputting data to the outside comprising a first transistor with a first conductive type which is connected between an output low voltage corresponding to a first logical value and the pad and which connects the output low voltage to the pad when the digital data has the first logical value; a second transistor with a second conductive type which is connected between an output high voltage corresponding to a second logical value and the pad and which connects the output high voltage to the pad when the digital data has the second logical value; and a third transistor with the first conductive type which is connected between the output high voltage and the pad so as to be parallel to the second transistor and which connects the output high voltage to the pad when the digital data has the second logical value.

    摘要翻译： 本公开涉及一种向外部输出数据的装置，包括具有第一导电类型的第一晶体管，第一晶体管连接在对应于第一逻辑值的输出低电压和焊盘之间，并且当数字数据被连接时，将输出低电压连接到焊盘 具有第一个逻辑值; 具有第二导电类型的第二晶体管，其连接在对应于第二逻辑值的输出高电压和焊盘之间，并且当数字数据具有第二逻辑值时，将输出高电压连接到焊盘; 以及具有第一导电类型的第三晶体管，其连接在输出高电压和焊盘之间，以便平行于第二晶体管并且当数字数据具有第二逻辑值时将输出高电压连接到焊盘。

    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
    4.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
    半导体集成电路设备

    公开(公告)号：US20080151640A1

    公开(公告)日：2008-06-26

    申请号：US11953319

    申请日：2007-12-10

    申请人： Eiichi MAKINO ,  Shigeo Ohshima

    发明人： Eiichi MAKINO ,  Shigeo Ohshima

    IPC分类号： G11C16/06

    CPC分类号： G11C16/26 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1063 ,  G11C2207/105

    摘要： This disclosure concerns a device outputting data to the outside comprising a first transistor with a first conductive type which is connected between an output low voltage corresponding to a first logical value and the pad and which connects the output low voltage to the pad when the digital data has the first logical value; a second transistor with a second conductive type which is connected between an output high voltage corresponding to a second logical value and the pad and which connects the output high voltage to the pad when the digital data has the second logical value; and a third transistor with the first conductive type which is connected between the output high voltage and the pad so as to be parallel to the second transistor and which connects the output high voltage to the pad when the digital data has the second logical value.

    摘要翻译： 本公开涉及一种向外部输出数据的装置，包括具有第一导电类型的第一晶体管，第一晶体管连接在对应于第一逻辑值的输出低电压和焊盘之间，并且当数字数据被连接时，将输出低电压连接到焊盘 具有第一个逻辑值; 具有第二导电类型的第二晶体管，其连接在对应于第二逻辑值的输出高电压和焊盘之间，并且当数字数据具有第二逻辑值时，将输出高电压连接到焊盘; 以及具有第一导电类型的第三晶体管，其连接在输出高电压和焊盘之间，以便平行于第二晶体管并且当数字数据具有第二逻辑值时将输出高电压连接到焊盘。

    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
    5.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 审中-公开
    非易失性半导体存储器件

    公开(公告)号：US20070206399A1

    公开(公告)日：2007-09-06

    申请号：US11682478

    申请日：2007-03-06

    申请人： Eiichi Makino ,  Koji Hosono ,  Kazushige Kanda ,  Shigeo Ohshima

    发明人： Eiichi Makino ,  Koji Hosono ,  Kazushige Kanda ,  Shigeo Ohshima

    IPC分类号： G11C5/02 ,  G11C5/06

    CPC分类号： G11C5/025 ,  G11C5/063 ,  G11C16/0483 ,  H01L2224/06155 ,  H01L2224/06156 ,  H01L2224/48227 ,  H01L2924/15311

    摘要： A nonvolatile semiconductor memory device having a first memory cell array including a plurality of electrical reprogramming and erasable nonvolatile semiconductor memory cells formed in a first area of a semiconductor substrate, a second memory cell array including a plurality of electrical reprogramming and erasable nonvolatile semiconductor memory cells formed in a second area different from said first area of said semiconductor substrate, said first and second memory cell arrays being arranged in a first direction, and a first pad section for inputting data to and outputting data from said first memory cell array and said second memory cell array, said first pad section having a plurality of pads arranged between said first memory cell array and said second memory cell array along a second direction perpendicular to said first direction.

    摘要翻译： 一种具有第一存储单元阵列的非易失性半导体存储器件，包括形成在半导体衬底的第一区域中的多个电重新编程和可擦除非易失性半导体存储单元，第二存储单元阵列包括多个电重编程和可擦除非易失性半导体存储单元 形成在与所述半导体衬底的所述第一区域不同的第二区域中，所述第一和第二存储单元阵列沿第一方向布置;以及第一焊盘区段，用于向所述第一存储单元阵列和所述第二存储单元阵列输入数据并输出数据 所述第一焊盘部分具有沿垂直于所述第一方向的第二方向布置在所述第一存储单元阵列和所述第二存储单元阵列之间的多个焊盘。

    Nonvolatile semiconductor memory device and nonvolatile semiconductor memory system
    6.
    发明授权
    Nonvolatile semiconductor memory device and nonvolatile semiconductor memory system 有权
    非易失性半导体存储器件和非易失性半导体存储器系统

    公开(公告)号：US07986557B2

    公开(公告)日：2011-07-26

    申请号：US12533529

    申请日：2009-07-31

    申请人： Naoya Tokiwa ,  Shigeo Ohshima

    发明人： Naoya Tokiwa ,  Shigeo Ohshima

    IPC分类号： G11C16/04 ,  G11C5/14

    CPC分类号： G11C16/30 ,  G11C5/143 ,  G11C5/145 ,  G11C8/06 ,  G11C8/10 ,  G11C16/0483

    摘要： A memory may include word lines; bit lines; cells provided corresponding to intersections between the word lines and the bit lines; sense amplifiers detecting data; a column decoder selecting a certain bit line for the sense amplifiers to output read data or receive write data; a row decoder configured to select a certain word line; a charge pump supplying power to the sense amplifiers, the column decoder, and the row decoder; a logic circuit controlling the sense amplifiers, the column decoder, and the row decoder based on an address selecting the memory cells; a first power source input applying a voltage to the logic circuit; and a second power source input applying a voltage higher than a voltage of the first power source input to the charge pump, and to supply power to the charge pump at least at a data reading time and a data writing time.

    摘要翻译： 存储器可以包括字线; 位线 对应于字线和位线之间的交点提供的单元; 感测放大器检测数据; 选择用于读出放大器的特定位线以输出读取数据或接收写入数据的列解码器; 行解码器，被配置为选择某个字线; 电荷泵向读出放大器，列解码器和行解码器供电; 基于选择存储器单元的地址来控制读出放大器，列解码器和行解码器的逻辑电路; 向逻辑电路施加电压的第一电源输入; 以及施加比所述第一电源输入的电压高于所述电荷泵的电压的第二电源输入，以及至少在数据读取时和数据写入时间向所述电荷泵供电。

    Semiconductor integrated circuit and memory system
    7.
    发明授权
    Semiconductor integrated circuit and memory system 有权
    半导体集成电路和存储器系统

    公开(公告)号：US06768691B2

    公开(公告)日：2004-07-27

    申请号：US10241908

    申请日：2002-09-12

    申请人： Noriyasu Kumazaki ,  Keiji Maruyama ,  Shigeo Ohshima

    发明人： Noriyasu Kumazaki ,  Keiji Maruyama ,  Shigeo Ohshima

    IPC分类号： G11C700

    CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/1066

    摘要： A semiconductor integrated circuit, comprising: a first output driving part which outputs a data signal in sync with a reference clock signal; a second output driving part which outputs a data strobe signal prescribing a timing of said data signal; and a driving control part which separately controls driving ability of said first and second output driving parts.

    摘要翻译： 一种半导体集成电路，包括：第一输出驱动部，其与参考时钟信号同步地输出数据信号; 第二输出驱动部，其输出规定所述数据信号的定时的数据选通信号; 以及分别控制所述第一和第二输出驱动部的驱动能力的驱动控制部。

    Semiconductor memory device capable of masking data to be written
    8.
    发明授权
    Semiconductor memory device capable of masking data to be written 失效

    公开(公告)号：US06483772B2

    公开(公告)日：2002-11-19

    申请号：US09951230

    申请日：2001-09-12

    申请人： Susumu Ozawa ,  Shigeo Ohshima ,  Katsumi Abe

    发明人： Susumu Ozawa ,  Shigeo Ohshima ,  Katsumi Abe

    IPC分类号： G11C800

    CPC分类号： G11C7/1087 ,  G11C7/1006 ,  G11C7/1078

    摘要： A specifying circuit specifies either the first masking method or the second masking method. A first generation circuit generates a signal corresponding to the first method. A second generation circuit generates a signal corresponding to the second method. A third generation circuit generates a write pulse signal on the basis of the output signal of the first generation circuit in response to the specification of the first masking method made by the specifying circuit and on the basis of the output signal of the second generation circuit in response to the specification of the second masking method made by the specifying circuit.

    Fast cycle RAM and data readout method therefor
    9.
    发明授权
    Fast cycle RAM and data readout method therefor 失效
    快速循环RAM及其数据读出方法

    公开(公告)号：US06426915B2

    公开(公告)日：2002-07-30

    申请号：US09749008

    申请日：2000-12-27

    申请人： Shigeo Ohshima ,  Nobuo Watanabe

    发明人： Shigeo Ohshima ,  Nobuo Watanabe

    IPC分类号： G11C800

    CPC分类号： G11C7/1066 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/22 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/409

    摘要： A row access command and column access command are supplied as one packet to an FCRAM in two successive clock cycles in order to shorten random access time and random cycle time. At this time, definition of the read/write operation is made by use of a first command and a decode address of a memory cell array is fetched in response to the first command. When the decode address of the memory cell array is fetched in response to the first command, command control pins of the conventional SDR/DDR-SDRAM are used as address pins.

    摘要翻译： 行访问命令和列访问命令在两个连续的时钟周期中作为一个分组提供给FCRAM，以便缩短随机访问时间和随机周期时间。 此时，通过使用第一命令来进行读/写操作的定义，并且响应于第一命令获取存储单元阵列的解码地址。 当响应于第一命令获取存储单元阵列的解码地址时，常规SDR / DDR-SDRAM的命令控制引脚用作地址引脚。

    Clock control circuit with an input stop circuit
    10.
    发明授权
    Clock control circuit with an input stop circuit 有权
    具有输入停止电路的时钟控制电路

    公开(公告)号：US06198690B1

    公开(公告)日：2001-03-06

    申请号：US09503000

    申请日：2000-02-14

    申请人： Koji Kato ,  Masahiro Kamoshida ,  Shigeo Ohshima

    发明人： Koji Kato ,  Masahiro Kamoshida ,  Shigeo Ohshima

    IPC分类号： G11C800

    CPC分类号： G11C7/225 ,  G06F1/10 ,  G11C7/22 ,  G11C7/222 ,  H03K5/135

    摘要： A clock control circuit includes a forward pulse delay circuit including a plurality of delay circuits for delaying a forward pulse signal FCL, a backward pulse delay circuit including a plurality of delay circuits for delaying a backward pulse signal RCL, a state-hold section including a plurality of state-hold circuits for controlling the operation of the backward pulse delay circuit in accordance with the transmission condition of the forward pulse signal in the forward pulse delay circuit, and an input stop circuit for stopping inputting a pulse corresponding to an external clock signal to the backward pulse delay circuit during a predetermined period from the time point when the external clock signal begins to be supplied.

    摘要翻译： 时钟控制电路包括：正向脉冲延迟电路，包括用于延迟正向脉冲信号FCL的多个延迟电路;包括用于延迟反向脉冲信号RCL的多个延迟电路的反向脉冲延迟电路;状态保持部分，包括： 多个状态保持电路，用于根据正向脉冲延迟电路中的正向脉冲信号的发送条件控制反向脉冲延迟电路的操作;以及输入停止电路，用于停止输入对应于外部时钟信号的脉冲 在从外部时钟信号开始供给的时刻起的规定期间内向后向脉冲延迟电路发送。