公开(公告)号：US20240090335A1

公开(公告)日：2024-03-14

申请号：US18307633

申请日：2023-04-26

Applicant: EVERSPIN TECHNOLOGIES, INC.

Inventor： Renu WHIG ,  Phillip MATHER ,  Kenneth SMITH ,  Sanjeev AGGARWAL ,  Jon SLAUGHTER ,  Nicholas RIZZO

IPC: H10N50/01 ,  B82Y25/00 ,  G01R33/00 ,  G01R33/09 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80 ,  H10N59/00

CPC classification number: H10N50/01 ,  B82Y25/00 ,  G01R33/0052 ,  G01R33/09 ,  G01R33/093 ,  G01R33/098 ,  H10B61/00 ,  H10N50/10 ,  H10N50/80 ,  H10N59/00

Abstract: A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a “Z” axis magnetic field onto sensors orientated in the XY plane.

公开(公告)号：US20210265563A1

公开(公告)日：2021-08-26

申请号：US17245882

申请日：2021-04-30

Applicant: EVERSPIN TECHNOLOGIES, INC.

Inventor： Renu WHIG ,  Phillip MATHER ,  Kenneth SMITH ,  Sanjeev AGGARWAL ,  Jon SLAUGHTER ,  Nicholas RIZZO

IPC: H01L43/12 ,  B82Y25/00 ,  G01R33/00 ,  G01R33/09 ,  H01L27/22 ,  H01L43/08 ,  H01L43/02

Abstract: A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a “Z” axis magnetic field onto sensors orientated in the XY plane.

公开(公告)号：US20190173004A1

公开(公告)日：2019-06-06

申请号：US16202496

申请日：2018-11-28

Applicant: Everspin Technologies, Inc.

Inventor： Sarin A. DESHPANDE ,  Jon SLAUGHTER ,  Cong HAI ,  Hyunwoo YANG ,  Naganivetha THIYAGARAJAH ,  Shukai YE

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02 ,  H01L43/10

Abstract: A method of fabricating a magnetoresistive device includes etching a magnetoresistive stack using a first etching process to form one or more sidewalls, and etching the stack using a second etching process after forming the one or more sidewalls. Wherein, the second etching process may be relatively more isotropic than the first etching process.

公开(公告)号：US20190123268A1

公开(公告)日：2019-04-25

申请号：US16230031

申请日：2018-12-21

Applicant: EVERSPIN TECHNOLOGIES, INC.

Inventor： Renu WHIG ,  Jijun SUN ,  Nicholas RIZZO ,  Jon SLAUGHTER ,  Dimitri HOUSSAMEDDINE ,  Frederick MANCOFF

IPC: H01L43/12 ,  G11C11/16 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: A magnetoresistive element (e.g., a spin-torque magnetoresistive memory element) includes a fixed magnetic layer, a free magnetic layer, having a high-iron alloy interface region located along a surface of the free magnetic layer, wherein the high-iron alloy interface region has at least 50% iron by atomic composition, and a first dielectric, disposed between the fixed magnetic layer and the free magnetic layer. The magnetoresistive element further includes a second dielectric, having a first surface that is in contact with the surface of the free magnetic layer, and an electrode, disposed between the second dielectric and a conductor. The electrode includes: (i) a non-ferromagnetic portion having a surface that is in contact with a second surface of the second dielectric, and (ii) a second portion having at least one ferromagnetic material disposed between the non-ferromagnetic portion of the electrode and the conductor.

公开(公告)号：US20190115060A1

公开(公告)日：2019-04-18

申请号：US16157315

申请日：2018-10-11

Applicant: Everspin Technologies, Inc.

Inventor： Sarin DESHPANDE ,  Sanjeev AGGARWAL ,  Jason JANESKY ,  Jon SLAUGHTER ,  Phillip LOPRESTI

IPC: G11C11/16 ,  H01F10/32 ,  H01L27/22 ,  H01L43/02

CPC classification number: G11C11/161 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  H01F10/3254 ,  H01F10/3272 ,  H01F10/3286 ,  H01F10/329 ,  H01L27/228 ,  H01L43/02

Abstract: Spin-orbit-torque (SOT) control strip lines are provided along the sides of free layers in perpendicular magnetic tunnel junction devices. Current flowing through such SOT control strip lines injects spin current into the free layers such that spin torque is applied to the free layers. The spin torque can be used to force the magnetic state of the free layer to a particular state based on the direction of the current through the SOT control strip line. In other embodiments, the SOT provides an assist to spin-transfer torque generated by current flowing vertically through the magnetic tunnel junction. Some embodiments have dedicated strip lines for a single magnetic tunnel junction such that a three-terminal device results. Other embodiments have multiple magnetic tunnel junctions sharing a strip line, where the strip line can be used to reset all of the magnetic tunnel junctions to the same state and can also be used as an assist such that individual magnetic tunnel junctions can be written using selection circuitry.

公开(公告)号：US20180122495A1

公开(公告)日：2018-05-03

申请号：US15852678

申请日：2017-12-22

Applicant: Everspin Technologies Inc.

Inventor： Thomas ANDRE ,  Jon SLAUGHTER ,  Dimitri HOUSSAMEDDINE ,  Syed M. ALAM

IPC: G11C29/50 ,  G11C11/16 ,  G06F11/08 ,  G06F11/10 ,  G11C29/04

CPC classification number: G11C29/50 ,  G06F11/08 ,  G06F11/1048 ,  G11C11/1673 ,  G11C2029/0411

Abstract: In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells. For instance, the memory device may be configured to identify a shorted bit cell within a memory array and to store the data in the memory array, such that a state of the data bit stored in the shorted bit cell matches the state associated with the shorted bit cell.

公开(公告)号：US20170263300A1

公开(公告)日：2017-09-14

申请号：US15605508

申请日：2017-05-25

Applicant: EVERSPIN TECHNOLOGIES, INC.

Inventor： Thomas ANDRE ,  Dimitri HOUSSAMEDDINE ,  Syed M. ALAM ,  Jon SLAUGHTER ,  Chitra SUBRAMANIAN

IPC: G11C11/16 ,  G06F12/0804

CPC classification number: G11C11/1675 ,  G06F12/0804 ,  G11C11/1677 ,  Y02D10/13

Abstract: A memory device is configured to identify a set of bit cells to be changed from a first state to a second state. In some examples, the memory device may apply a first voltage to the set of bit cells to change a least a first portion of the set of bit cells to the second state. In some cases, the memory device may also identify a second portion of the bit cells that remained in the first state following the application of the first voltage. In these cases, the memory device may apply a second voltage having a greater magnitude, duration, or both to the second portion of the set of bit cells in order to set the second portion of bit cells to the second state.

公开(公告)号：US20170117461A1

公开(公告)日：2017-04-27

申请号：US15388650

申请日：2016-12-22

Applicant: EVERSPIN TECHNOLOGIES, INC.

Inventor： Renu WHIG ,  Phillip MATHER ,  Kenneth SMITH ,  Sanjeev AGGARWAL ,  Jon SLAUGHTER ,  Nicholas RIZZO

IPC: H01L43/12 ,  G01R33/00 ,  H01L27/22 ,  G01R33/09 ,  H01L43/08 ,  H01L43/02

CPC classification number: H01L43/12 ,  B82Y25/00 ,  G01R33/0052 ,  G01R33/09 ,  G01R33/093 ,  G01R33/098 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08

Abstract: A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a “Z” axis magnetic field onto sensors orientated in the XY plane.

公开(公告)号：US20240397731A1

公开(公告)日：2024-11-28

申请号：US18792891

申请日：2024-08-02

Applicant: Everspin Technologies, Inc.

Inventor： Jijun SUN ,  Sanjeev AGGARWAL ,  Han-Jong CHIA ,  Jon SLAUGHTER ,  Renu WHIG

IPC: H10B61/00 ,  G11B5/39 ,  G11C11/16 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

Abstract: A magnetoresistive stack, including an electrically conductive material, and a seed region disposed above the electrically conductive material and including chromium (Cr). A chromium content of the seed region is large enough to render the seed region substantially non-magnetic. The magnetoresistive stack includes a fixed magnetic region disposed above the seed region. The fixed magnetic region includes a synthetic antiferromagnetic structure including a first ferromagnetic region disposed above the seed region, a coupling layer disposed on and in contact with the first ferromagnetic region, and a second ferromagnetic region disposed on and in contact with the coupling layer. The magnetoresistive stack includes one or more dielectric layers disposed above the second ferromagnetic region, and a free magnetic region disposed above the one or more dielectric layers.

公开(公告)号：US20190386212A1

公开(公告)日：2019-12-19

申请号：US16551952

申请日：2019-08-27

Applicant: Everspin Technologies, Inc.

Inventor： Renu WHIG ,  Jijun SUN ,  Nicholas RIZZO ,  Jon SLAUGHTER ,  Dimitri HOUSSAMEDDINE ,  Frederick MANCOFF

IPC: H01L43/12 ,  G11C11/16 ,  H01L43/10 ,  H01L43/02 ,  H01L43/08

Abstract: A magnetoresistive element (e.g., a spin-torque magnetoresistive memory element) includes a fixed magnetic layer, a free magnetic layer, having a high-iron alloy interface region located along a surface of the free magnetic layer, wherein the high-iron alloy interface region has at least 50% iron by atomic composition, and a first dielectric, disposed between the fixed magnetic layer and the free magnetic layer. The magnetoresistive element further includes a second dielectric, having a first surface that is in contact with the surface of the free magnetic layer, and an electrode, disposed between the second dielectric and a conductor. The electrode includes: (i) a non-ferromagnetic portion having a surface that is in contact with a second surface of the second dielectric, and (ii) a second portion having at least one ferromagnetic material disposed between the non-ferromagnetic portion of the electrode and the conductor.