-
公开(公告)号：US10255961B2
公开(公告)日：2019-04-09
申请号：US15851816
申请日：2017-12-22
Applicant: Everspin Technologies, Inc.
Inventor： Han-Jong Chia , Sumio Ikegawa , Michael Tran , Jon Slaughter
Abstract: A magnetoresistive memory device that stores data in the synthetic antiferromagnet (SAF) included in each spin-torque memory cell provides for more robust data storage. In normal operation, the memory cells use the free portion of the memory cell for data storage. Techniques for storing data in the reference portions of memory cells are presented, where an unbalanced SAF that includes ferromagnetic layers having different magnetic moments is used to lower the switching barrier for the SAF and allow for writing data values to the SAF using lower currents and magnetic fields than would be required for a balanced SAF.
-
公开(公告)号：US10199122B2
公开(公告)日：2019-02-05
申请号：US15852678
申请日：2017-12-22
Applicant: Everspin Technologies Inc.
Inventor： Thomas Andre , Jon Slaughter , Dimitri Houssameddine , Syed M. Alam
Abstract: In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells. For instance, the memory device may be configured to identify a shorted bit cell within a memory array and to store the data in the memory array, such that a state of the data bit stored in the shorted bit cell matches the state associated with the shorted bit cell.
-
公开(公告)号：US20180205396A1
公开(公告)日：2018-07-19
申请号：US15846242
申请日：2017-12-19
Applicant: Everspin Technologies Inc.
Inventor： Sumio Ikegawa , Jon Slaughter
CPC classification number: H03M13/2906 , G06F11/1048 , G06F11/1068 , G06F11/167 , G11C29/52
Abstract: Techniques for recovering preprogrammed data from non-volatile memory are provided that include majority voting and/or use of one or more levels of ECC correction. Embodiments include storage of multiple copies of the data where ECC correction is performed before and after majority voting with respect to the multiple copies. Multiple levels of ECC correction can also be performed where one level of ECC is performed at the local level (e.g. on-chip), whereas another level of ECC correction is performed at a system level.
-
公开(公告)号：US09773970B2
公开(公告)日：2017-09-26
申请号：US15041178
申请日：2016-02-11
Applicant: EVERSPIN TECHNOLOGIES, INC.
Inventor： Phillip Mather , Jon Slaughter , Nicholas Rizzo
CPC classification number: H01L43/02 , G01R33/098 , H01L27/22 , H01L43/08 , H01L43/12
Abstract: A magnetic field sensor including a first plurality and a second plurality of magnetoresistive sensors, wherein each magnetoresistive sensor of the first plurality and the second plurality of magnetoresistive sensors comprises: an electrode; a reference layer adjacent to the electrode, wherein the reference layer includes a synthetic antiferromagnetic structure; a magnetic sense element; and an intermediate layer between the reference layer and the magnetic sense element; and one or more conductors configured to electrically couple the magnetoresistive sensors of the first plurality and the second plurality in various configurations.
-
公开(公告)号：US09679627B2
公开(公告)日：2017-06-13
申请号：US14502367
申请日：2014-09-30
Applicant: Everspin Technologies, Inc.
Inventor： Thomas Andre , Dimitri Houssameddine , Syed M. Alam , Jon Slaughter , Chitra Subramanian
IPC: G11C16/04 , G11C11/16 , G06F12/0804
CPC classification number: G11C11/1675 , G06F12/0804 , G11C11/1677 , Y02D10/13
Abstract: A memory device is configured to identify a set of bit cells to be changed from a first state to a second state. In some examples, the memory device may apply a first voltage to the set of bit cells to change a least a first portion of the set of bit cells to the second state. In some cases, the memory device may also identify a second portion of the bit cells that remained in the first state following the application of the first voltage. In these cases, the memory device may apply a second voltage having a greater magnitude, duration, or both to the second portion of the set of bit cells in order to set the second portion of bit cells to the second state.
-
Patent Agency Ranking
公开(公告)号：US09548095B2
公开(公告)日：2017-01-17
申请号：US14697577
申请日：2015-04-27
Applicant: Everspin Technologies, Inc.
Inventor： Dimitri Houssameddine , Jon Slaughter
CPC classification number: G11C11/161 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1695 , G11C11/1697 , G11C29/70 , G11C29/74 , G11C29/838 , G11C2213/78 , G11C2213/79
Abstract: Memory cells in a spin-torque magnetic random access memory (MRAM) include at least two magnetic tunnel junctions within each memory cell, where each memory cell only stores a single data bit of information. Access circuitry coupled to the memory cells are able to read from and write to a memory cell even when one of the magnetic tunnel junctions within the memory cell is defective and is no longer functional. Self-referenced and referenced reads can be used in conjunction with the multiple magnetic tunnel junction memory cells. In some embodiments, writing to the memory cell forces all magnetic tunnel junctions into a known state, whereas in other embodiments, a subset of the magnetic tunnel junctions are forced to a known state.
Abstract translation: 自旋扭矩磁随机存取存储器（MRAM）中的存储单元包括每个存储器单元内的至少两个磁性隧道结，其中每个存储器单元仅存储单个数据位的信息。 耦合到存储器单元的访问电路即使当存储单元内的磁隧道结之一有缺陷并且不再起作用时，也能够读取和写入存储单元。 自参考和参考读取可以与多个磁性隧道结存储器单元结合使用。 在一些实施例中，向存储器单元的写入迫使所有磁隧道结进入已知状态，而在其它实施例中，磁性隧道结的子集被强制为已知状态。
-
公开(公告)号：US09419208B2
公开(公告)日：2016-08-16
申请号：US15046483
申请日：2016-02-18
Applicant: Everspin Technologies, Inc.
Inventor： Renu Whig , Jijun Sun , Nicholas Rizzo , Jon Slaughter , Dimitri Houssameddine , Frederick Mancoff
CPC classification number: H01L43/12 , G11C11/161 , H01L43/02 , H01L43/08 , H01L43/10
Abstract: A magnetoresistive memory element (e.g., a spin-torque magnetoresistive memory element) includes a fixed magnetic layer, a free magnetic layer having perpendicular magnetic anisotropy, and a first dielectric, disposed between the fixed magnetic layer and the free magnetic layer. A first surface of the first dielectric is in contact with a first surface of the free magnetic layer. The magnetoresistive memory element further includes a second dielectric, having a first surface that is in contact with a second surface of the free magnetic layer, a conductor, including electrically conductive material, and an electrode, disposed between the second dielectric and the conductor. The electrode includes: (i) a non-ferromagnetic portion having a surface that is in contact with a second surface of the second dielectric, and (ii) a second portion including at least one ferromagnetic material disposed between the non-ferromagnetic portion of the electrode and the conductor.
Abstract translation: 磁阻存储元件（例如，自旋转矩磁阻存储元件）包括固定磁性层，具有垂直磁各向异性的自由磁性层和设置在固定磁性层和自由磁性层之间的第一电介质。 第一电介质的第一表面与自由磁性层的第一表面接触。 磁阻存储元件还包括第二电介质，其具有与自由磁性层的第二表面接触的第一表面，包括导电材料的导体以及设置在第二电介质和导体之间的电极。 电极包括：（i）具有与第二电介质的第二表面接触的表面的非铁磁部分，和（ii）第二部分，其包括设置在第二电介质的非铁磁部分之间的至少一个铁磁材料 电极和导体。
-
公开(公告)号：US09362491B2
公开(公告)日：2016-06-07
申请号：US14954075
申请日：2015-11-30
Applicant: EVERSPIN TECHNOLOGIES, INC.
Inventor： Renu Whig , Phillip Mather , Kenneth Smith , Sanjeev Aggarwal , Jon Slaughter , Nicholas Rizzo
CPC classification number: H01L43/12 , B82Y25/00 , G01R33/0052 , G01R33/09 , G01R33/093 , G01R33/098 , H01L27/22 , H01L43/02 , H01L43/08
Abstract: A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a “Z” axis magnetic field onto sensors orientated in the XY plane.
Abstract translation: 半导体工艺集成了三个桥接电路，每个电路包括在单个芯片上作为惠斯登电桥耦合的磁阻传感器，以在三个正交方向上感测磁场。 该过程包括形成磁阻传感器的各种沉积和蚀刻步骤以及在三个桥接电路中的一个上的多个通量引导器，用于将“Z”轴磁场传送到在XY平面中定向的传感器上。
-
公开(公告)号：US20160093354A1
公开(公告)日：2016-03-31
申请号：US14502287
申请日：2014-09-30
Applicant: Everspin Technologies, Inc.
Inventor： Thomas Andre , Jon Slaughter , Dimitri Houssameddine , Syed M. Alam
CPC classification number: G11C29/50 , G06F11/08 , G06F11/1048 , G11C11/1673 , G11C2029/0411
Abstract: In some examples, a memory device may be configured to store data in either an original or an inverted state based at least in part on a state associated with one or more shorted bit cells. For instance, the memory device may be configured to identify a shorted bit cell within a memory array and to store the data in the memory array, such that a state of the data bit stored in the shorted bit cell matches the state associated with the shorted bit cell.
Abstract translation: 在一些示例中，存储器设备可以被配置为至少部分地基于与一个或多个短路位单元相关联的状态来存储处于原始或反相状态的数据。 例如，存储器设备可以被配置为识别存储器阵列内的短路位单元并且将数据存储在存储器阵列中，使得存储在短路位单元中的数据位的状态与短路相关联的状态匹配 位单元格。
-
公开(公告)号：US11758823B2
公开(公告)日：2023-09-12
申请号：US16188934
申请日：2018-11-13
Applicant: Everspin Technologies, Inc.
Inventor： Jijun Sun , Jon Slaughter , Renu Whig
Abstract: A magnetically free region of magnetoresistive device includes at least a first ferromagnetic region and a second ferromagnetic region separated by a non-magnetic insertion region. At least one of the first ferromagnetic region and the second ferromagnetic region may include at least a boron-rich ferromagnetic layer positioned proximate a boron-free ferromagnetic layer.
-
-
-
-
-
-
-
-
-
Search Results
75
records
(took 0.026 seconds)
