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11.发明授权Magnetoresistive structure having two dielectric layers, and method of manufacturing same 有权具有两个电介质层的磁阻结构及其制造方法公开(公告)号：US09548442B2
公开(公告)日：2017-01-17
申请号：US14797172
申请日：2015-07-12
Applicant: Everspin Technologies, Inc.
Inventor： Sanjeev Aggarwal , Kerry Nagel , Jason Janesky
CPC classification number: H01L43/12 , G11C11/161 , H01L43/02 , H01L43/08 , H01L43/10
Abstract: A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least an encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes.
Abstract translation: 具有两个电介质层的磁阻结构及其制造方法包括位于两个电介质层之间的自由磁性层。 制造方法包括至少两个蚀刻工艺和至少一个介于其间的封装工艺，其中在蚀刻工艺之间形成在部分形成的磁阻堆叠的侧壁上的封装。
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公开(公告)号：US09525129B2
公开(公告)日：2016-12-20
申请号：US15142721
申请日：2016-04-29
Applicant: EVERSPIN TECHNOLOGIES, INC.
Inventor： Renu Whig , Phillip Mather , Kenneth Smith , Sanjeev Aggarwal , Jon Slaughter , Nicholas Rizzo
CPC classification number: H01L43/12 , B82Y25/00 , G01R33/0052 , G01R33/09 , G01R33/093 , G01R33/098 , H01L27/22 , H01L43/02 , H01L43/08
Abstract: A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a “Z” axis magnetic field onto sensors orientated in the XY plane.
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13.发明申请公开(公告)号：US20160315253A1
公开(公告)日：2016-10-27
申请号：US15147682
申请日：2016-05-05
Applicant: Everspin Technologies, Inc.
Inventor： Sarin A. Deshpande , Sanjeev Aggarwal , Kerry Joseph Nagel , Chaitanya Mudivarthi , Nicholas Rizzo , Jason Allen Janesky
CPC classification number: H01L43/12 , H01L27/222 , H01L43/08
Abstract: In forming a top electrode for a magnetoresistive device, photoresist used in patterning the electrode is stripped using a non-reactive stripping process. Such a non-reactive stripping process uses water vapor or some other non-oxidizing gas that also passivates exposed portions the magnetoresistive device. In such magnetoresistive devices, a non-reactive spacer layer is included that helps prevent diffusion between layers in the magnetoresistive device, where the non-reactive nature of the spacer layer prevents sidewall roughness that can interfere with accurate formation of the lower portions of the magnetoresistive device.
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14.发明申请TOP ELECTRODE COUPLING IN A MAGNETORESISTIVE DEVICE USING AN ETCH STOP LAYER 有权使用蚀刻停止层的磁性器件中的顶部电极耦合公开(公告)号：US20150357559A1
公开(公告)日：2015-12-10
申请号：US14297389
申请日：2014-06-05
Applicant: Everspin Technologies, Inc.
Inventor： Kerry Joseph Nagel , Sanjeev Aggarwal , Moazzem Hossain , Nicholas Rizzo
CPC classification number: H01L27/222 , G11C11/161 , H01L43/02 , H01L43/08 , H01L43/12
Abstract: A layer of silicon nitride above the bottom electrode and on the sidewalls of the magnetoresistive stack serves as an insulator and an etch stop during manufacturing of a magnetoresistive device. Non-selective chemical mechanical polishing removes any silicon nitride overlying a top electrode for the device along with silicon dioxide used for encapsulation. Later etching operations corresponding to formation of a via to reach the top electrode use selective etching chemistries that remove silicon dioxide to access the top electrode, but do not remove silicon nitride. Thus, the silicon nitride acts as an etch stop, and, in the resulting device, provides an insulating layer that prevents unwanted short circuits between the via and the bottom electrode and between the via and the sidewalls of the magnetoresistive device stack.
Abstract translation: 在磁阻堆叠的底部电极和侧壁上方的氮化硅层用作磁阻器件的制造期间的绝缘体和蚀刻停止。 非选择性化学机械抛光除了用于器件的顶部电极以及用于封装的二氧化硅之外的任何氮化硅。 对应于形成通孔以到达顶部电极的后来的蚀刻操作使用去除二氧化硅以进入顶部电极但是不去除氮化硅的选择性蚀刻化学品。 因此，氮化硅用作蚀刻停止，并且在所得到的器件中提供了防止通孔和底部电极之间以及磁阻器件堆叠的通路和侧壁之间的不期望的短路的绝缘层。
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15.发明申请NON-REACTIVE PHOTORESIST REMOVAL AND SPACER LAYER OPTIMIZATION IN A MAGNETORESISTIVE DEVICE 有权磁性装置中的非反应性光电离层去除和间隔层优化公开(公告)号：US20150236249A1
公开(公告)日：2015-08-20
申请号：US14296189
申请日：2014-06-04
Applicant: Everspin Technologies, Inc.
Inventor： Sarin A. Deshpande , Kerry Joseph Nagel , Sanjeev Aggarwal , Chaitanya Mudivarthi
CPC classification number: H01L43/12 , H01L27/222 , H01L43/08
Abstract: In forming a top electrode for a magnetoresistive device, photoresist used in patterning the electrode is stripped using a non-reactive stripping process. Such a non-reactive stripping process uses water vapor or some other non-oxidizing gas that also passivates exposed portions the magnetoresistive device. In such magnetoresistive devices, a non-reactive spacer layer is included that helps prevent diffusion between layers in the magnetoresistive device, where the non-reactive nature of the spacer layer prevents sidewall roughness that can interfere with accurate formation of the lower portions of the magnetoresistive device.
Abstract translation: 在形成用于磁阻器件的顶部电极时，使用非反应性剥离工艺剥离用于图案化电极的光致抗蚀剂。 这种非反应性汽提方法使用水蒸汽或一些其它非氧化气体，其也钝化了磁阻装置的暴露部分。 在这种磁阻器件中，包括非反应性间隔层，其有助于防止磁阻器件中的层之间的扩散，其中间隔层的非反应性质防止可能干扰磁阻的下部的精确形成的侧壁粗糙度 设备。
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Patent Agency Ranking
公开(公告)号：US20150102006A1
公开(公告)日：2015-04-16
申请号：US14296153
申请日：2014-06-04
Applicant: Everspin Technologies, Inc.
Inventor： Chaitanya Mudivarthi , Sarin A. Deshpande , Sanjeev Aggarwal
IPC: H01L41/47
CPC classification number: H01L43/12 , G11B5/3163 , G11C11/161 , H01L27/222 , H01L27/228 , H01L43/02 , H01L43/08 , Y10T29/49021
Abstract: Isolation of magnetic layers in the magnetoresistive stack is achieved by passivation of sidewalls of the magnetic layers or deposition of a thin film of non-magnetic dielectric material on the sidewalls prior to subsequent etching steps. Etching the magnetic layers using a non-reactive gas further prevents degradation of the sidewalls.
Abstract translation: 通过在后续蚀刻步骤之前钝化磁性层的侧壁或在侧壁上沉积非磁性介电材料的薄膜来实现磁阻堆叠中的磁性层的隔离。 使用非反应性气体蚀刻磁性层进一步防止侧壁的劣化。
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公开(公告)号：US20140190933A1
公开(公告)日：2014-07-10
申请号：US13826658
申请日：2013-03-14
Applicant: Everspin Technologies, Inc.
Inventor： Sarin Deshpande , Sanjeev Aggarwal , Kerry Nagel
IPC: G11B5/127
CPC classification number: G11B5/127 , G11C11/161 , H01L43/12 , Y10T29/49052
Abstract: A method of manufacturing a magnetoresistive-based device includes a metal hard mask that is inert to a top electrode etch chemistry and that has low sputter yield during a magnetic stack sputter. The metal hard mask is patterned by the photo resist and the photo mask is then stripped and the top electrode (overlying magnetic materials of the magnetoresistive-based device) is patterned by the metal hard mask.
Abstract translation: 制造基于磁阻的器件的方法包括对顶部电极蚀刻化学物质是惰性的并且在磁堆栈溅射期间具有低的溅射产率的金属硬掩模。 金属硬掩模由光致抗蚀剂构图，然后剥离光掩模，并且通过金属硬掩模对顶部电极（基于磁阻的装置的覆盖磁性材料）进行图案化。
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公开(公告)号：US20140138346A1
公开(公告)日：2014-05-22
申请号：US13972637
申请日：2013-08-21
Applicant: EverSpin Technologies, Inc.
Inventor： Renu Whig , Philip Mather , Kenneth Smith , Sanjeev Aggarwal , Jon Slaughter , Nicholas Rizzo
CPC classification number: H01L43/12 , B82Y25/00 , G01R33/0052 , G01R33/09 , G01R33/093 , G01R33/098 , H01L27/22 , H01L43/02 , H01L43/08
Abstract: A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a “Z” axis magnetic field onto sensors orientated in the XY plane.
Abstract translation: 半导体工艺集成了三个桥接电路，每个电路包括在单个芯片上作为惠斯登电桥耦合的磁阻传感器，以在三个正交方向上感测磁场。 该过程包括形成磁阻传感器的各种沉积和蚀刻步骤以及在三个桥接电路中的一个上的多个通量引导器，用于将“Z”轴磁场传送到在XY平面中定向的传感器上。
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公开(公告)号：US12167702B2
公开(公告)日：2024-12-10
申请号：US18123729
申请日：2023-03-20
Applicant: Everspin Technologies, Inc.
Inventor： Sumio Ikegawa , Han Kyu Lee , Sanjeev Aggarwal , Jijun Sun , Syed M. Alam , Thomas Andre
Abstract: The present disclosure is drawn to, among other things, a magnetoresistive device and a magnetoresistive memory comprising a plurality of such magnetoresistive devices. In some aspects, a magnetoresistive device may include a magnetically fixed region, a magnetically free region above or below the magnetically fixed region, and an intermediate region positioned between the magnetically fixed region and the magnetically free region, wherein the intermediate region includes a first dielectric material. The magnetoresistive device may also include encapsulation layers formed on opposing side walls of the magnetically free region, wherein the encapsulation layers include the first dielectric material.
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公开(公告)号：US12075630B2
公开(公告)日：2024-08-27
申请号：US18045539
申请日：2022-10-11
Applicant: Everspin Technologies, Inc.
Inventor： Kerry Joseph Nagel , Sanjeev Aggarwal , Thomas Andre , Sarin A. Deshpande
CPC classification number: H10B61/00 , G11C11/161 , H10N50/01 , H10N50/10 , H10N50/80
Abstract: Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.
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