公开(公告)号：US08710579B1

公开(公告)日：2014-04-29

申请号：US13551237

申请日：2012-07-17

Applicant: Fredrick Jenne ,  Krishnaswamy Ramkumar

Inventor： Fredrick Jenne ,  Krishnaswamy Ramkumar

IPC: H01L29/792

CPC classification number: H01L21/28282 ,  G11C16/04 ,  H01L21/022 ,  H01L21/02323 ,  H01L27/11563 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/792

Abstract: A semiconductor device and method of manufacturing the same are provided. In one embodiment, semiconductor device comprises a split charge-trapping region comprising two nitride layers with charge traps distributed therein, the two nitride layers separated by one or more oxide layers. The two nitride layers include a first nitride layer closer to a substrate over which the split charge-trapping region is formed, and a second nitride layer on the other side of the one or more oxide layers. The second nitride layer comprises a majority of the charge traps. Other embodiments are also described.

Abstract translation: 提供半导体器件及其制造方法。 在一个实施例中，半导体器件包括分离的电荷捕获区域，其包括分布有电荷陷阱的两个氮化物层，两个氮化物层由一个或多个氧化物层分隔开。 两个氮化物层包括更靠近其上形成有分离电荷捕获区的衬底的第一氮化物层和在一个或多个氧化物层的另一侧上的第二氮化物层。 第二氮化物层包括大部分电荷阱。 还描述了其它实施例。

公开(公告)号：US20130175600A1

公开(公告)日：2013-07-11

申请号：US13431069

申请日：2012-03-27

Applicant: Fredrick Jenne ,  Krishnaswamy Ramkumar

Inventor： Fredrick Jenne ,  Krishnaswamy Ramkumar

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L29/792 ,  B82Y10/00 ,  H01L21/28282 ,  H01L29/513 ,  H01L29/785 ,  H01L29/7926

Abstract: Embodiments of a non-planar memory device including a split charge-trapping region and methods of forming the same are described. Generally, the device comprises: a channel formed from a thin film of semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide overlying the channel; a split charge-trapping region overlying the tunnel oxide, the split charge-trapping region including a bottom charge-trapping layer comprising a nitride closer to the tunnel oxide, and a top charge-trapping layer, wherein the bottom charge-trapping layer is separated from the top charge-trapping layer by a thin anti-tunneling layer comprising an oxide. Other embodiments are also disclosed.

Abstract translation: 描述了包括分离电荷捕获区域的非平面存储器件及其形成方法的实施例。 通常，该器件包括：由覆盖存储器件的源极和漏极的衬底上的表面的半导体材料薄膜形成的沟道; 覆盖通道的隧道氧化物; 分离电荷捕获区域，覆盖隧道氧化物，分离电荷捕获区域包括底部电荷捕获层，其包含更接近隧道氧化物的氮化物，以及顶部电荷捕获层，其中底部电荷捕获层被分离 从顶部的电荷捕获层通过包含氧化物的薄的抗隧道层。 还公开了其他实施例。

公开(公告)号：US20130178031A1

公开(公告)日：2013-07-11

申请号：US13436878

申请日：2012-03-31

Applicant: Krishnaswamy Ramkumar ,  Fredrick Jenne ,  Sagy Levy

Inventor： Krishnaswamy Ramkumar ,  Fredrick Jenne ,  Sagy Levy

IPC: H01L21/336

CPC classification number: H01L29/7833 ,  B82Y10/00 ,  H01L21/28282 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/7836 ,  H01L29/7843 ,  H01L29/792 ,  H01L29/7926

Abstract: An embodiment of a method of integrating a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming in a first region of a substrate a channel of a memory device from a semiconducting material overlying a surface of the substrate, the channel connecting a source and a drain of the memory device; forming a charge trapping dielectric stack over the channel adjacent to a plurality of surfaces of the channel, wherein the charge trapping dielectric stack includes a blocking layer on a charge trapping layer over a tunneling layer; and forming a MOS device over a second region of the substrate.

Abstract translation: 描述了将非易失性存储器件集成到逻辑MOS流中的方法的实施例。 通常，该方法包括：在衬底的第一区域中形成存储器件的通道，覆盖衬底表面的半导体材料，连接存储器件的源极和漏极的沟道; 在与所述通道的多个表面相邻的所述通道上形成电荷捕获电介质堆叠，其中所述电荷捕获电介质堆叠包括在隧道层上的电荷捕获层上的阻挡层; 以及在所述衬底的第二区域上形成MOS器件。

公开(公告)号：US08222688B1

公开(公告)日：2012-07-17

申请号：US12767105

申请日：2010-04-26

Applicant: Fredrick Jenne ,  Krishnaswamy Ramkumar

Inventor： Fredrick Jenne ,  Krishnaswamy Ramkumar

IPC: H01L29/792

CPC classification number: H01L21/28282 ,  G11C16/04 ,  H01L21/022 ,  H01L21/02323 ,  H01L27/11563 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/792

Abstract: A semiconductor device includes a substrate, a first oxide layer formed on the substrate, an oxygen-rich nitride layer formed on the first oxide layer, a second oxide layer formed on the oxygen-rich nitride layer, and an oxygen-poor nitride layer formed on the second oxide layer.

Abstract translation: 半导体器件包括衬底，形成在衬底上的第一氧化物层，形成在第一氧化物层上的富氧氮化物层，形成在富氧氮化物层上的第二氧化物层和形成的不透氧氮化物层 在第二氧化物层上。

公开(公告)号：US20090179253A1

公开(公告)日：2009-07-16

申请号：US11811958

申请日：2007-06-13

Applicant: Sagy Levy ,  Krishnaswamy Ramkumar ,  Fredrick Jenne ,  Sam Geha

Inventor： Sagy Levy ,  Krishnaswamy Ramkumar ,  Fredrick Jenne ,  Sam Geha

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L21/0214 ,  C23C16/0272 ,  C23C16/308 ,  G11C16/0466 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/3145 ,  H01L27/11568 ,  H01L29/40117 ,  H01L29/518 ,  H01L29/7833 ,  H01L29/792

Abstract: A semiconductor device including an oxide-nitride-oxide (ONO) structure having a multi-layer charge storing layer and methods of forming the same are provided. Generally, the method involves: (i) forming a first oxide layer of the ONO structure; (ii) forming a multi-layer charge storing layer comprising nitride on a surface of the first oxide layer; and (iii) forming a second oxide layer of the ONO structure on a surface of the multi-layer charge storing layer. Preferably, the charge storing layer comprises at least two silicon oxynitride layers having differing stoichiometric compositions of Oxygen, Nitrogen and/or Silicon. More preferably, the ONO structure is part of a silicon-oxide-nitride-oxide-silicon (SONOS) structure and the semiconductor device is a SONOS memory transistor. Other embodiments are also disclosed.

Abstract translation: 提供了包括具有多层电荷存储层的氧化物 - 氧化物 - 氧化物（ONO）结构的半导体器件及其形成方法。 通常，该方法包括：（i）形成ONO结构的第一氧化物层; （ii）在所述第一氧化物层的表面上形成包含氮化物的多层电荷存储层; 和（iii）在多层电荷存储层的表面上形成ONO结构的第二氧化物层。 优选地，电荷存储层包括至少两个氧氮，氮和/或硅具有不同化学计量组成的氮氧化硅层。 更优选地，ONO结构是氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）结构的一部分，并且半导体器件是SONOS存储晶体管。 还公开了其他实施例。

公开(公告)号：US08445381B2

公开(公告)日：2013-05-21

申请号：US11961750

申请日：2007-12-20

Applicant: Krishnaswamy Ramkumar ,  Sundar Narayanan

Inventor： Krishnaswamy Ramkumar ,  Sundar Narayanan

IPC: H01L21/02

CPC classification number: H01L21/022 ,  H01L21/0217 ,  H01L21/02233 ,  H01L21/02337 ,  H01L21/28044 ,  H01L21/3144 ,  H01L29/4941 ,  H01L29/78

Abstract: A method of making a semiconductor structure comprises forming an oxide layer on a substrate; forming a silicon nitride layer on the oxide layer; annealing the layers in NO; and annealing the layers in ammonia. The equivalent oxide thickness of the oxide layer and the silicon nitride layer together is at most 25 Angstroms.

Abstract translation: 制造半导体结构的方法包括在衬底上形成氧化物层; 在氧化物层上形成氮化硅层; 在NO中退火层; 并在氨中退火层。 氧化物层和氮化硅层的等效氧化物厚度在一起为至多25埃。

公开(公告)号：US08143129B2

公开(公告)日：2012-03-27

申请号：US12185747

申请日：2008-08-04

Applicant: Krishnaswamy Ramkumar ,  Ravindra Kapre ,  Jeremy Warren

Inventor： Krishnaswamy Ramkumar ,  Ravindra Kapre ,  Jeremy Warren

IPC: H01L29/792

CPC classification number: H01L29/7833 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7836 ,  H01L29/7843

Abstract: A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device.

Abstract translation: 一种半导体结构及其形成方法。 半导体结构包括具有设置在第一区域上的非易失性电荷陷阱存储器件和设置在第二区域上的逻辑器件的衬底。 可以在形成逻辑器件的阱和通道之后形成电荷陷阱电介质叠层。 可以避免HF预清洗和SC1清洁，以提高非挥发性电荷陷阱存储器件的阻挡层的质量。 在逻辑MOS栅极绝缘体层的热氧化或氮化期间，阻挡层可以被热再氧化或氮化，以致密封阻挡层。 可以使用多层衬垫来首先在高压逻辑器件中偏置源极和漏极注入，并且还阻挡非易失性电荷陷阱存储器件的硅化。

公开(公告)号：US07898852B1

公开(公告)日：2011-03-01

申请号：US12005803

申请日：2007-12-27

Applicant: Sagy Levy ,  Krishnaswamy Ramkumar ,  Peter Voss

Inventor： Sagy Levy ,  Krishnaswamy Ramkumar ,  Peter Voss

IPC: G11C16/04

CPC classification number: G11C16/0466 ,  G11C11/56 ,  H01L21/28282 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/7881 ,  H01L29/792

Abstract: Methods and apparatus for programming and sensing a bi-nitride layer trapped-charge memory device in one of a first and second programmed states or one of a first and second erased states, where the first and second programmed states correspond to first and second uniform trapped charge distributions of a first charge type and the first and second erased states correspond to first and second uniform trapped charge distributions of a second charge type.

Abstract translation: 用于以第一和第二编程状态或第一和第二擦除状态中的一种编程和感测二氮化物层捕获电荷存储器件的方法和装置，其中第一和第二编程状态对应于第一和第二均匀捕获 第一充电类型和第一和第二擦除状态的电荷分布对应于第二充电类型的第一和第二均匀俘获电荷分布。

公开(公告)号：US07867918B1

公开(公告)日：2011-01-11

申请号：US12046073

申请日：2008-03-11

Applicant: Krishnaswamy Ramkumar

Inventor： Krishnaswamy Ramkumar

IPC: H01L21/31

CPC classification number: H01L21/28282 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02233 ,  H01L21/02271 ,  H01L21/28202 ,  H01L21/28273 ,  H01L21/3143 ,  H01L29/513 ,  H01L29/518

Abstract: A semiconductor topography is provided which includes a silicon dioxide layer with a thickness equal to or less than approximately 10 angstroms and a silicon nitride layer arranged upon the silicon dioxide layer. In addition, a method is provided which includes growing an oxide film upon a semiconductor topography in the presence of an ozonated substance and depositing a silicon nitride film upon the oxide film. In some embodiments, the method may include growing the oxide film in a first chamber at a first temperature and transferring the semiconductor topography from the first chamber to a second chamber while the semiconductor topography is exposed to a substantially similar temperature as the first temperature. In either embodiment, the method may be used to form a semiconductor device including an oxide-nitride gate dielectric having an electrical equivalent oxide gate dieletric thickness of less than approximately 20 angstroms.

Abstract translation: 提供半导体形貌，其包括厚度等于或小于约10埃的二氧化硅层和布置在二氧化硅层上的氮化硅层。 此外，提供了一种方法，其包括在存在臭氧化物质的情况下在半导体形貌上生长氧化膜并在氧化物膜上沉积氮化硅膜。 在一些实施例中，该方法可以包括在第一温度下在第一室中生长氧化膜并将半导体形貌从第一室转移到第二室，同时将半导体形貌暴露于与第一温度基本相似的温度。 在任一实施例中，该方法可用于形成半导体器件，其包括具有小于约20埃的电等效氧化物栅极薄膜厚度的氧化物 - 氮化物栅极电介质。

公开(公告)号：US07670963B2

公开(公告)日：2010-03-02

申请号：US11904513

申请日：2007-09-26

Applicant: Krishnaswamy Ramkumar ,  Sagy Levy

Inventor： Krishnaswamy Ramkumar ,  Sagy Levy

IPC: H01L21/469

CPC classification number: H01L21/28282 ,  H01L21/3144 ,  H01L21/3145 ,  H01L29/4234 ,  H01L29/66833 ,  Y10S438/954

Abstract: A method for fabricating a nonvolatile charge trap memory device is described. The method includes first forming a tunnel dielectric layer on a substrate in a first process chamber of a single-wafer cluster tool. A charge-trapping layer is then formed on the tunnel dielectric layer in a second process chamber of the single-wafer cluster tool. A top dielectric layer is then formed on the charge-trapping layer in the second or in a third process chamber of the single-wafer cluster tool.

Abstract translation: 描述了制造非易失性电荷陷阱存储器件的方法。 该方法包括首先在单晶片簇工具的第一处理室中的衬底上形成隧道电介质层。 然后在单晶片簇工具的第二处理室中的隧道介电层上形成电荷捕获层。 然后在单晶片簇工具的第二或第三处理室中的电荷俘获层上形成顶部电介质层。