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    DUAL LINER SILICIDE
    12.
    发明申请
    DUAL LINER SILICIDE 有权
    双层硅胶

    公开(公告)号：US20160372380A1

    公开(公告)日：2016-12-22

    申请号：US14740987

    申请日：2015-06-16

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc

    发明人： Balasubramanian Pranatharthiharan ,  Ruilong Xie ,  Chun-Chen Yeh

    IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/417 ,  H01L29/66

    CPC分类号： H01L21/823871 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/823864 ,  H01L23/5226 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/41725 ,  H01L29/456 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628

    摘要： A method for fabricating a dual silicide device includes growing source and drain (S/D) regions for an N-type device, forming a protection layer over a gate structure and the S/D regions of the N-type device and growing S/D regions for a P-type device. A first dielectric layer is conformally deposited and portions removed to expose the S/D regions. Exposed S/D regions for the P-type device are silicided to form a liner. A second dielectric layer is conformally deposited. A dielectric fill is formed over the second dielectric layer. Contact holes are opened through the second dielectric layer to expose the liner for the P-type device and expose the protection layer for the N-type device. The S/D regions for the N-type device are exposed by opening the protection layer. Exposed S/D regions adjacent to the gate structure are silicided to form a liner for the N-type device. Contacts are formed.

    摘要翻译： 制造双硅化物器件的方法包括：生长用于N型器件的源极和漏极（S / D）区域，在栅极结构上形成保护层，并且在N型器件的S / D区域上生长S / D区域用于P型设备。 第一电介质层被共形沉积，部分被去除以暴露S / D区域。 用于P型器件的暴露的S / D区域被硅化以形成衬垫。 第二电介质层被共形沉积。 在第二电介质层上形成电介质填充物。 接触孔通过第二介电层打开，露出P型器件的衬垫，露出N型器件的保护层。 通过打开保护层来暴露N型器件的S / D区域。 暴露的与栅极结构相邻的S / D区域被硅化以形成用于N型器件的衬垫。 触点形成。

    Process for integrated circuit fabrication including a uniform depth tungsten recess technique
    13.
    发明授权
    Process for integrated circuit fabrication including a uniform depth tungsten recess technique 有权
    集成电路制造工艺，包括均匀的深度钨凹陷技术

    公开(公告)号：US09502302B2

    公开(公告)日：2016-11-22

    申请号：US14512700

    申请日：2014-10-13

    申请人： STMicroelectronics, Inc. ,  GlobalFoundries Inc ,  International Business Machines Corporation

    发明人： Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

    IPC分类号： H01L21/8234 ,  H01L29/423

    CPC分类号： H01L29/42376 ,  H01L21/82345 ,  H01L21/823456 ,  H01L27/088 ,  H01L29/42372 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/78

    摘要： Dummy gates are removed from a pre-metal layer to produce a first opening (with a first length) and a second opening (with a second length longer than the first length). Work function metal for a metal gate electrode is provided in the first and second openings. Tungsten is deposited to fill the first opening and conformally line the second opening, thus leaving a third opening. The thickness of the tungsten layer substantially equals the length of the first opening. The third opening is filled with an insulating material. The tungsten is then recessed in both the first and second openings using a dry etch to substantially a same depth from a top surface of the pre-metal layer to complete the metal gate electrode. Openings left following the recess operation are then filled with a dielectric material forming a cap on the gate stack which includes the metal gate electrode.

    摘要翻译： 从预金属层去除虚拟门以产生具有第一长度的第一开口和第二开口（具有长于第一长度的第二长度）。 用于金属栅电极的功函数金属设置在第一和第二开口中。 沉积钨以填充第一开口并保形地排列第二开口，从而留下第三个开口。 钨层的厚度基本上等于第一开口的长度。 第三个开口填充绝缘材料。 然后使用干蚀刻将钨从第一和第二开口凹入到与金属前层的顶表面基本相同的深度以完成金属栅电极。 然后在凹槽操作之后留下的开口填充有在包括金属栅电极的栅堆叠上形成盖的电介质材料。

    Dual channel finFET with relaxed pFET region
    14.
    发明授权
    Dual channel finFET with relaxed pFET region 有权
    具有松弛pFET区域的双通道finFET

    公开(公告)号：US09496185B2

    公开(公告)日：2016-11-15

    申请号：US14670800

    申请日：2015-03-27

    申请人： International Business Machines Corporation ,  GLOBALFOUNDRIES, Inc. ,  STMICROELECTRONICS, INC.

    发明人： Xiuyu Cai ,  Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

    IPC分类号： H01L27/12 ,  H01L21/84 ,  H01L29/78

    CPC分类号： H01L21/845 ,  H01L27/1211 ,  H01L29/7849

    摘要： Fabricating a semiconductor device includes providing a strained semiconductor material (SSM) layer disposed on a dielectric layer, forming a first plurality of fins on the SSOI structure, at least one fin of the first plurality of fins is in a nFET region and at least one fin is in a pFET region, etching portions of the dielectric layer under portions of the SSM layer of the at least one fin in the pFET region, filling areas cleared by the etching, forming a second plurality of fins from the at least one fin in the nFET region such that each fin comprises a portion of the SSM layer disposed on the dielectric layer, and forming a third plurality of fins from the at least one fin in the pFET region such that each fin comprises a portion of the SSM layer disposed on a flowable oxide.

    摘要翻译： 制造半导体器件包括提供设置在电介质层上的应变半导体材料（SSM）层，在SSOI结构上形成第一多个鳍片，第一组多个鳍片中的至少一个鳍片在nFET区域中，并且至少一个 鳍状物在pFET区域中，在pFET区域中的至少一个鳍片的SSM层的部分之下蚀刻介电层的部分，通过蚀刻清除的填充区域，从至少一个鳍片形成第二多个鳍片 所述nFET区域使得每个鳍片包括设置在所述电介质层上的所述SSM层的一部分，以及从所述pFET区域中的所述至少一个翅片形成第三多个翅片，使得每个翅片包括设置在所述SSM层上的部分 可流动的氧化物。

    Macro to monitor n-p bump
    15.
    发明授权
    Macro to monitor n-p bump 有权
    宏观监控n-p凸点

    公开(公告)号：US09460969B1

    公开(公告)日：2016-10-04

    申请号：US14669055

    申请日：2015-03-26

    申请人： International Business Machines Corporation ,  Globalfoundries, Inc. ,  STMicroelectronics, Inc.

    发明人： Xiuyu Cai ,  Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

    IPC分类号： H01L21/66 ,  H01L21/8238 ,  H01L21/768 ,  H01L21/308 ,  H01L21/306

    CPC分类号： H01L21/823871 ,  H01L21/30625 ,  H01L21/3085 ,  H01L21/82385 ,  H01L22/12 ,  H01L22/30

    摘要： A technique relates to fabricating a macro for measurements utilized in dual spacer, dual epitaxial transistor devices. The macro is fabricated according to a fabrication process. The macro is a test layout of a semiconductor structure having n-p bumps at junctions between NFET areas and PFET areas. Optical critical dimension (OCD) spectroscopy is performed to obtain the measurements of the n-p bumps on the macro. An amount of chemical mechanical polishing is determined to remove the n-p bumps on the macro based on the measurements of the n-p bumps on the macro. Chemical mechanical polishing is performed to remove the n-p bumps on the macro. The amount previously determined for the macro is utilized to perform chemical mechanical polishing for each of the dual spacer, dual epitaxial layer transistor devices having been fabricated under the fabrication process of the macro in which the fabrication process produced the n-p bumps.

    摘要翻译： 技术涉及制造用于双间隔物，双外延晶体管器件中的测量的宏。 宏是根据制造工艺制造的。 该宏是在NFET区域和PFET区域之间的结处具有n-p个凸起的半导体结构的测试布局。 执行光临界尺度（OCD）光谱以获得宏观上的n-p凸块的测量。 基于宏观上的n-p凸块的测量，确定了一定量的化学机械抛光以去除宏观上的n-p凸块。 进行化学机械抛光以除去宏观上的n-p凸块。 先前为宏确定的量用于对在制造工艺产生n-p个凸块的宏的制造过程中制造的每个双间隔物，双外延层晶体管器件进行化学机械抛光。

    Buried source-drain contact for integrated circuit transistor devices and method of making same
    17.
    发明授权
    Buried source-drain contact for integrated circuit transistor devices and method of making same 有权
    集成电路晶体管器件的埋地源极 - 漏极接触及其制作方法

    公开(公告)号：US09385201B2

    公开(公告)日：2016-07-05

    申请号：US14297822

    申请日：2014-06-06

    申请人： STMicroelectronics, Inc. ,  GlobalFoundries Inc ,  International Business Machines Corporation

    发明人： Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh ,  Xiuyu Cai ,  William J. Taylor

    IPC分类号： H01L21/84 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66

    CPC分类号： H01L21/823475 ,  H01L21/28518 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

    摘要： An integrated circuit transistor is formed on a substrate. A trench in the substrate is at least partially filed with a metal material to form a source (or drain) contact buried in the substrate. The substrate further includes a source (or drain) region in the substrate which is in electrical connection with the source (or drain) contact. The substrate further includes a channel region adjacent to the source (or drain) region. A gate dielectric is provided on top of the channel region and a gate electrode is provided on top of the gate dielectric. The substrate may be of the silicon on insulator (SOI) or bulk type. The buried source (or drain) contact makes electrical connection to a side of the source (or drain) region using a junction provided at a same level of the substrate as the source (or drain) and channel regions.

    摘要翻译： 在基板上形成集成电路晶体管。 衬底中的沟槽至少部分地与金属材料填充以形成埋在衬底中的源极（或漏极）接触。 衬底还包括与源极（或漏极）接触电连接的衬底中的源极（或漏极）区域。 衬底还包括与源极（或漏极）区域相邻的沟道区域。 栅极电介质设置在沟道区域的顶部，栅电极设置在栅极电介质的顶部。 衬底可以是绝缘体上硅（SOI）或体积型。 埋入的源极（或漏极）接触器使用与源极（或漏极）和沟道区域在基底的相同水平处提供的接点，使得与源极（或漏极）区域的一侧电连接。

    TEST MACRO FOR USE WITH A MULTI-PATTERNING LITHOGRAPHY PROCESS
    19.
    发明申请
    TEST MACRO FOR USE WITH A MULTI-PATTERNING LITHOGRAPHY PROCESS 有权
    使用多模式图像处理的测试方法

    公开(公告)号：US20150140697A1

    公开(公告)日：2015-05-21

    申请号：US14607160

    申请日：2015-01-28

    申请人： International Business Machines Corporation ,  GlobalFoundries, Inc.

    发明人： Tenko Yamashita ,  Chun-Chen Yeh ,  Jin Cho ,  Hui Zang

    IPC分类号： H01L21/66 ,  H01L21/8234

    CPC分类号： H01L22/14 ,  G03F7/70466 ,  H01L21/823431 ,  H01L22/10 ,  H01L22/12 ,  H01L22/34

    摘要： A method for forming an integrated circuit having a test macro using a multiple patterning lithography process (MPLP) is provided. The method includes forming an active area of the test macro having a first and second gate region during a first step of MPLP, and forming a first and second source/drain regions in the active area during a second step of the MPLP. The method also includes forming a first contact connected to the first gate region, a second contact connected to the second gate region, a third contact connected to the first source/drain region, and a forth contact connected to the source/drain region and determining if an overlay shift occurred between the first step and the second step of the step of the MPLP by testing for a short between one or more of the first contact, the second contact, the third contact, or the fourth contact.

    摘要翻译： 提供了一种使用多重图案化光刻工艺（MPLP）形成具有测试宏的集成电路的方法。 该方法包括在MPLP的第一步骤期间形成具有第一和第二栅极区的测试宏的有源区，以及在MPLP的第二步骤期间在有源区中形成第一和第二源/漏区。 该方法还包括形成连接到第一栅极区域的第一触点，连接到第二栅极区域的第二触点，连接到第一源极/漏极区域的第三触点和连接到源极/漏极区域的第四触点和确定 如果通过测试第一接触，第二接触，第三接触或第四接触中的一个或多个之间的短路，在MPLP的步骤的第一步骤和第二步骤之间发生覆盖移位。

    Dual liner silicide
    20.
    发明授权
    Dual liner silicide 有权

    公开(公告)号：US10395995B2

    公开(公告)日：2019-08-27

    申请号：US15956082

    申请日：2018-04-18

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

    发明人： Balasubramanian Pranatharthiharan ,  Ruilong Xie ,  Chun-Chen Yeh

    IPC分类号： H01L21/8238 ,  H01L29/66 ,  H01L27/092 ,  H01L29/417 ,  H01L29/08 ,  H01L29/45 ,  H01L23/522 ,  H01L21/768 ,  H01L21/285

    摘要： A method for fabricating a dual silicide device includes growing source and drain (S/D) regions for an N-type device, forming a protection layer over a gate structure and the S/D regions of the N-type device and growing S/D regions for a P-type device. A first dielectric layer is conformally deposited and portions removed to expose the S/D regions. Exposed S/D regions for the P-type device are silicided to form a liner. A second dielectric layer is conformally deposited. A dielectric fill is formed over the second dielectric layer. Contact holes are opened through the second dielectric layer to expose the liner for the P-type device and expose the protection layer for the N-type device. The S/D regions for the N-type device are exposed by opening the protection layer. Exposed S/D regions adjacent to the gate structure are silicided to form a liner for the N-type device. Contacts are formed.