公开(公告)号：US09299745B2

公开(公告)日：2016-03-29

申请号：US14272916

申请日：2014-05-08

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xunyuan Zhang ,  Sean Xuan Lin ,  Kunaljeet Tanwar

IPC: H01L21/02 ,  H01L27/22 ,  H01L43/12 ,  H01L43/08 ,  H01L43/02

CPC classification number: H01L27/222 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: Integrated circuits with magnetic tunnel junction (MTJ) structures and methods for fabricating integrated circuits with MTJ structures are provided. An exemplary method for fabricating an integrated circuit includes forming a first conductive line in electrical connection with an underlying semiconductor device. The method exposes a surface of the first conductive line. Further, the method selectively deposits a conductive material on the surface of the first conductive line to form an electrode contact. The method includes forming a MTJ structure over the electrode contact.

Abstract translation: 提供了具有磁隧道结（MTJ）结构的集成电路和用于制造具有MTJ结构的集成电路的方法。 用于制造集成电路的示例性方法包括形成与下面的半导体器件电连接的第一导线。 该方法暴露第一导线的表面。 此外，该方法选择性地将导电材料沉积在第一导电线的表面上以形成电极接触。 该方法包括在电极接触件上形成MTJ结构。

公开(公告)号：US10580696B1

公开(公告)日：2020-03-03

申请号：US16106246

申请日：2018-08-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sean Xuan Lin ,  Christian Witt ,  Mark V. Raymond ,  Nicholas V. LiCausi ,  Errol Todd Ryan

IPC: H01L23/12 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768 ,  H01L23/532 ,  H01L21/288

Abstract: Structures for interconnects and methods of forming interconnects. An interconnect opening in a dielectric layer includes a first portion and a second portion arranged over the first portion. A first conductor layer composed of a first metal is arranged inside the first portion of the interconnect opening. A second conductor layer composed of a second metal is arranged inside the second portion of the interconnect opening. The first metal is ruthenium.

公开(公告)号：US10573593B2

公开(公告)日：2020-02-25

申请号：US15983168

申请日：2018-05-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sean Xuan Lin ,  Xunyuan Zhang ,  Shao Beng Law ,  James Jay McMahon

IPC: H01L21/4763 ,  H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to metal interconnect structures for super (skip) via integration and methods of manufacture. The structure includes: a first wiring layer with one or more wiring structures; a second wiring layer including an interconnect and wiring structure; and at least one upper wiring layer with one or more via interconnect and wiring structures located above the second wiring layer. The one or more via interconnect and wiring structures partially including a first metal material and remaining portions with a conductive material over the first metal material. A skip via passes through the second wiring layer and extends to the one or more wiring structures of the first wiring layer. The skip via partially includes the metal material and remaining portions of the skip via includes the conductive material over the first metal material.

公开(公告)号：US10395926B1

公开(公告)日：2019-08-27

申请号：US15954736

申请日：2018-04-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Minghao Tang ,  Yuping Ren ,  Sean Xuan Lin ,  Shao Beng Law ,  Genevieve Beique ,  Xun Xiang ,  Rui Chen

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/768

Abstract: Methods of self-aligned multiple patterning. A mandrel line is formed over a hardmask layer, and forming a block mask is formed over a first portion of the mandrel line that is linearly arranged between respective second portions of the mandrel line. After forming the first block mask, the second portions of the mandrel line are removed with an etching process to cut the mandrel line and expose respective portions of the hardmask layer. A second portion of the mandrel line is covered by the block mask during the etching process to define a mandrel cut in the mandrel line.

公开(公告)号：US10181421B1

公开(公告)日：2019-01-15

申请号：US15647977

申请日：2017-07-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Errol Todd Ryan ,  Sean Xuan Lin

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528

Abstract: Devices and methods of fabricating devices are provided. One method includes: obtaining an intermediate semiconductor device having a dielectric layer, an insulating layer, and a plurality of metal lines, including a liner material and a first metal material; recessing the metal material of each metal line forming a set of cavities; filling the cavities with a protective cap; etching the protective cap and the liner material in the set of cavities; depositing a plurality of dielectric caps in the set of cavities; depositing an interlayer dielectric layer over the insulating layer and the plurality of dielectric caps; patterning a via in the interlayer dielectric layer; and depositing a lining and a second metal material in the interconnect area; wherein the second metal material is electrically insulated from the first metal in at least one of the plurality of metal lines.

公开(公告)号：US20160163601A1

公开(公告)日：2016-06-09

申请号：US14560102

申请日：2014-12-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Chanro Park ,  Sean Xuan Lin

IPC: H01L21/8234 ,  H01L21/3213 ,  H01L27/088 ,  H01L29/51 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L21/823468 ,  H01L21/02181 ,  H01L21/28088 ,  H01L21/32133 ,  H01L21/823456 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/42376 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628

Abstract: A method that involves forming a high-k gate insulation layer, a work-function adjusting metal layer and a metal protection layer in first and second replacement gate cavities, wherein the metal protection layer is formed so as to pinch-off the first gate cavity while leaving the second gate cavity partially un-filled, forming a first bulk conductive metal layer in the un-filled portion of the second gate cavity, removing substantially all of the metal protection layer in the first gate cavity while leaving a portion of the metal protection layer in the second gate cavity, forming a second conductive metal layer within the first and second replacement gate cavities, recessing the conductive metal layers so as to define first and second gate-cap cavities in the first and second replacement gate cavities, respectively, and forming gate cap layers within the first and second gate-cap cavities.

Abstract translation: 一种涉及在第一和第二替换栅腔中形成高k栅极绝缘层，功函数调整金属层和金属保护层的方法，其中金属保护层形成为夹住第一栅极腔 同时使第二栅极腔部分未填充，在第二栅极腔的未填充部分中形成第一体导电金属层，基本上除去第一栅极腔中的所有金属保护层，同时留下金属的一部分 在所述第二栅极腔中形成保护层，在所述第一和第二替代栅极腔内形成第二导电金属层，使所述导电金属层凹陷，以分别在所述第一和第二替换栅极腔中限定第一和第二栅极盖腔， 以及在所述第一和第二栅极盖腔内形成栅极盖层。

公开(公告)号：US20150325622A1

公开(公告)日：2015-11-12

申请号：US14272916

申请日：2014-05-08

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xunyuan Zhang ,  Sean Xuan Lin ,  Kunaljeet Tanwar

IPC: H01L27/22 ,  H01L43/08 ,  H01L43/02 ,  H01L43/12

CPC classification number: H01L27/222 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: Integrated circuits with magnetic tunnel junction (MTJ) structures and methods for fabricating integrated circuits with MTJ structures are provided. An exemplary method for fabricating an integrated circuit includes forming a first conductive line in electrical connection with an underlying semiconductor device. The method exposes a surface of the first conductive line. Further, the method selectively deposits a conductive material on the surface of the first conductive line to form an electrode contact. The method includes forming a MTJ structure over the electrode contact.

Abstract translation: 提供了具有磁隧道结（MTJ）结构的集成电路和用于制造具有MTJ结构的集成电路的方法。 用于制造集成电路的示例性方法包括形成与下面的半导体器件电连接的第一导线。 该方法暴露第一导线的表面。 此外，该方法选择性地将导电材料沉积在第一导电线的表面上以形成电极接触。 该方法包括在电极接触件上形成MTJ结构。