公开(公告)号：US09530833B2

公开(公告)日：2016-12-27

申请号：US14307078

申请日：2014-06-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Dina H. Triyoso ,  Sanford Chu ,  Johannes Mueller ,  Patrick Polakowski

IPC: H01L29/92 ,  H01L27/108 ,  H01L49/02 ,  H01L27/115 ,  H01L27/08

CPC classification number: H01L28/55 ,  H01L27/0805 ,  H01L27/1085 ,  H01L27/11502 ,  H01L28/40

Abstract: An illustrative method disclosed herein includes providing a semiconductor structure. The semiconductor structure includes a first interlayer dielectric provided over a semiconductor substrate. A first electrode of a first capacitor is formed over the first interlayer dielectric. A layer of first dielectric material is deposited over the first electrode of the first capacitor and the first interlayer dielectric. A layer of electrically conductive material is deposited over the layer of first dielectric material. A second electrode of the first capacitor and a first electrode of the second capacitor are formed from the layer of electrically conductive material. After the formation of the second electrode of the first capacitor and the first electrode of the second capacitor, a layer of second dielectric material is deposited and a second electrode of the second capacitor is formed over the layer of second dielectric material.

Abstract translation: 本文公开的说明性方法包括提供半导体结构。 半导体结构包括设置在半导体衬底上的第一层间电介质。 第一电容器的第一电极形成在第一层间电介质上。 第一电介质材料层沉积在第一电容器和第一层间电介质的第一电极上。 一层导电材料沉积在第一介电材料层上。 第一电容器的第二电极和第二电容器的第一电极由导电材料层形成。 在形成第一电容器的第二电极和第二电容器的第一电极之后，沉积第二电介质材料层，并且第二电容器的第二电极形成在第二电介质材料层上。

公开(公告)号：US20160064472A1

公开(公告)日：2016-03-03

申请号：US14835278

申请日：2015-08-25

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Lili Cheng ,  Dina H. Triyoso ,  Jeasung Park ,  David Paul Brunco ,  Robert Fox ,  Sanford Chu

IPC: H01L49/02 ,  G06F17/50 ,  H01L21/02 ,  H01L23/522 ,  H01L21/822

CPC classification number: H01L28/60 ,  G06F17/5068 ,  H01L21/02181 ,  H01L21/02189 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits including a MIMCAP device and methods of forming the integrated circuits are provided. An exemplary method of forming an integrated circuit including a MIMCAP device includes pre-determining a thickness of at least one of a bottom high-K layer or a top high-K layer of the MIMCAP device, followed by fabricating the MIMCAP device. The pre-determined thickness is established based upon a pre-determined TDDB lifetime for the MIMCAP device and a minimum target capacitance density at an applied voltage bias to be employed for the MIMCAP device. The MIMCAP device includes a bottom electrode and a dielectric layer disposed over the bottom electrode. The dielectric layer includes a stack of individual layers including the bottom high-K layer, the top high-K layer, and a lower-K layer sandwiched therebetween. At least one of the bottom high-K layer or the top high-K layer has the pre-determined thickness.

Abstract translation: 提供了包括MIMCAP器件的集成电路和形成集成电路的方法。 形成包括MIMCAP器件的集成电路的示例性方法包括预先确定MIMCAP器件的底部高K层或顶部高K层中的至少之一的厚度，然后制造MIMCAP器件。 预先确定的厚度是基于MIMCAP器件的预定的TDDB寿命和MIMCAP器件所采用的施加电压偏置下的最小目标电容密度而建立的。 MIMCAP器件包括设置在底部电极上的底部电极和电介质层。 电介质层包括层叠的各层，包括底部高K层，顶部高K层和夹在其间的下部K层。 底部高K层或顶部高K层中的至少一层具有预定厚度。

公开(公告)号：US09269785B2

公开(公告)日：2016-02-23

申请号：US14165209

申请日：2014-01-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Johannes Mueller ,  Dina H. Triyoso ,  Robert Binder ,  Joachim Metzger ,  Patrick Polakowski

IPC: H01L21/00 ,  H01L29/00 ,  H01L29/51 ,  H01L21/02 ,  H01L21/3105 ,  H01L27/115

CPC classification number: H01L29/516 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02266 ,  H01L21/0228 ,  H01L21/28291 ,  H01L21/3105 ,  H01L27/11507 ,  H01L29/511 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6684 ,  H01L29/78391

Abstract: The present disclosure provides a semiconductor device comprising a substrate, an undoped HfO2 layer formed over the substrate and a TiN layer formed on the HfO2 layer. Herein, the undoped HfO2 layer is at least partially ferroelectric. In illustrative methods for forming a semiconductor device, an undoped amorphous HfO2 layer is formed over a semiconductor substrate and a TiN layer is formed on the undoped amorphous HfO2 layer. A thermal annealing process is performed for at least partially inducing a ferroelectric phase in the undoped amorphous HfO2 layer.

Abstract translation: 本公开提供了一种半导体器件，其包括衬底，在衬底上形成的未掺杂的HfO 2层和形成在HfO 2层上的TiN层。 这里，未掺杂的HfO 2层至少部分为铁电体。 在用于形成半导体器件的说明性方法中，在半导体衬底上形成未掺杂的非晶HfO 2层，并且在未掺杂的非晶HfO 2层上形成TiN层。 进行热退火处理以至少部分地诱导未掺杂的无定形HfO 2层中的铁电相。

公开(公告)号：US09209186B1

公开(公告)日：2015-12-08

申请号：US14315885

申请日：2014-06-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mitsuhiro Togo ,  Changyong Xiao ,  Yiqun Liu ,  Dina H. Triyoso ,  Rohit Pal

IPC: H01L21/00 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/324 ,  H01L21/265 ,  H01L21/321 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/84 ,  H01L29/417

CPC classification number: H01L27/0922 ,  H01L21/26513 ,  H01L21/32115 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/845 ,  H01L27/0924 ,  H01L29/41791 ,  H01L29/49 ,  H01L29/4958 ,  H01L29/66545 ,  H01L29/66795

Abstract: A range of lowest, low and regular threshold voltages are provided to three p-type devices and three n-type devices co-fabricated on a same substrate. For the p-type devices, the range is achieved for the lowest using an additional thick layer of a p-type work function metal in a gate structure and oxidizing it, the low Vt is achieved with the thick p-type work function metal alone, and the regular Vt is achieved with a thinner layer of the p-type work function metal. For the n-type devices, the lowest Vt is achieved by implanting tantalum nitride with arsenic, argon, silicon or germanium and not adding any of the additional p-type work function metal in the gate structure, the low Vt is achieved by not adding the additional p-type work function metal, and the regular Vt is achieved with a thinnest layer of the p-type work function metal.

Abstract translation: 三个p型器件和在同一衬底上共同制造的三个n型器件提供了一个最低，低和规则阈值电压范围。 对于p型器件，使用栅极结构中的p型功函数金属的附加厚层并对其进行氧化来实现最低的范围，低Vt由厚的p型功函数金属单独实现 ，并且通过p型功函数金属的较薄层实现常规Vt。 对于n型器件，最低的Vt是通过用砷，氩，硅或锗注入氮化钽而不是在栅极结构中添加任何附加的p型功函数金属来实现的，低Vt是通过不添加 额外的p型功函数金属，而常规Vt是用最薄层的p型功函金属实现的。