公开(公告)号：US09935106B2

公开(公告)日：2018-04-03

申请号：US15088874

申请日：2016-04-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Edward J. Nowak ,  Brent A. Anderson ,  Robert R. Robison

IPC: H01L27/092 ,  H01L27/12 ,  H01L29/04 ,  H01L21/8238 ,  H01L21/84

CPC classification number: H01L27/092 ,  H01L21/823885 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/1203 ,  H01L29/045

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to multi-finger devices in multiple-gate-contacted-pitch, integrated structures and methods of manufacture. The structure includes: a first plurality of fin structures formed on a substrate having a channel surface in a {110} plane; and a second plurality of fin structures formed on the substrate with a channel surface in a {100} plane, positioned in relation to the first plurality of fin structures.

公开(公告)号：US20180012988A1

公开(公告)日：2018-01-11

申请号：US15678206

申请日：2017-08-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak

IPC: H01L29/78 ,  H01L29/10 ,  H01L27/12 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/3115 ,  H01L21/762

CPC classification number: H01L29/785 ,  H01L21/31155 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/1037 ,  H01L29/66621 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7849

Abstract: A semiconductor device including semiconductor material having a bend and a trench feature formed at the bend, and a gate structure at least partially disposed in the trench feature. A method of fabricating a semiconductor structure including forming a semiconductor material with a trench feature over a layer, forming a gate structure at least partially in the trench feature, and bending the semiconductor material such that stress is induced in the semiconductor material in an inversion channel region of the gate structure.

公开(公告)号：US20180006024A1

公开(公告)日：2018-01-04

申请号：US15198309

申请日：2016-06-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Brent A. Anderson ,  Edward J. Nowak

IPC: H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L21/823468 ,  H01L21/823487

Abstract: One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include a fin having a first source/drain region and a second source/drain, the first source/drain region being over a substrate and below a central region of the fin, and the second source/drain region being within a dielectric layer and over the central region of the fin; a gate structure within the dielectric layer substantially surrounding the central region of the fin between the first source/drain region and the second source drain region, wherein the fin includes at least one tapered region from the central region of the fin to at least one of the first source/drain region or the second source/drain region.

公开(公告)号：US09786751B2

公开(公告)日：2017-10-10

申请号：US15263551

申请日：2016-09-13

Applicant: GlobalFoundries Inc.

Inventor： Brent A. Anderson ,  Jeffrey B. Johnson ,  Edward J. Nowak

IPC: H01L29/78 ,  H01L23/48 ,  H01L21/8238 ,  H01L21/768 ,  H01L29/66 ,  H01L29/417 ,  H01L23/522 ,  H01L23/528 ,  H01L29/08

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/41775 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7851

Abstract: Disclosed are semiconductor structures comprising a field effect transistor (FET) having a low-resistance source/drain contact and, optionally, low gate-to-source/drain contact capacitance. The structures comprise a semiconductor body and, contained therein, first and second source/drain regions and a channel region. A first gate is adjacent to the semiconductor body at the channel region and a second, non-functioning, gate is adjacent to the semiconductor body such that the second source/drain region is between the first and second gates. First and second source/drain contacts are on the first and source/drain regions, respectively. The second source/drain contact is wider than the first and, thus, has a lower resistance. Additionally, spacing of the first and second source/drain contacts relative to the first gate can be such that the first gate-to-second source/drain contact capacitance is equal to or less than the first gate-to-first source/drain contact capacitance. Also disclosed are associated formation methods.

公开(公告)号：US20170287911A1

公开(公告)日：2017-10-05

申请号：US15088874

申请日：2016-04-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Edward J. Nowak ,  Brent A. Anderson ,  Robert R. Robison

IPC: H01L27/092 ,  H01L21/84 ,  H01L21/8238 ,  H01L27/12 ,  H01L29/04

CPC classification number: H01L27/092 ,  H01L21/823885 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/1203 ,  H01L29/045

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to multi-finger devices in multiple-gate-contacted-pitch, integrated structures and methods of manufacture. The structure includes: a first plurality of fin structures formed on a substrate having a channel surface in a {110} plane; and a second plurality of fin structures formed on the substrate with a channel surface in a {100} plane, positioned in relation to the first plurality of fin structures.

公开(公告)号：US09673055B2

公开(公告)日：2017-06-06

申请号：US14613416

申请日：2015-02-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak

IPC: H01L21/308 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L21/3086 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1211

Abstract: A method of single-fin removal for quadruple density fins. A first double density pattern of first sidewall spacers is produced on a semiconductor substrate from first mandrels formed by a first mask using a minimum pitch. A second double density pattern of second sidewall spacers is produced on a layer disposed above the first double density pattern from second mandrels formed by a second mask with a the minimum pitch that is shifted relative to the first mask. A single sidewall spacer is removed from either the first or second double density pattern of first and second sidewall spacers. Sidewall image transfer processes allow the formation of quadruple density fins from which but a single fin is removed.

公开(公告)号：US20170062609A1

公开(公告)日：2017-03-02

申请号：US15351753

申请日：2016-11-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Lyndon R. Logan ,  Edward J. Nowak ,  Robert R. Robison

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/4238 ,  H01L29/66545 ,  H01L29/66803 ,  H01L29/66818 ,  H01L29/7835 ,  H01L29/785

Abstract: Devices and methods for a high voltage FinFET with a shaped drift region include a lateral diffusion metal oxide semiconductor (LDMOS) FinFET having a substrate with a top surface and a fin attached to the top surface. The fin includes a source region having a first type of doping, an undoped gate-control region adjacent the source region, a drift region adjacent the undoped gate-control region opposite the source region, and a drain region. The amount of doping of the source region is greater than the amount of doping in the drift region. The drain region is adjacent to the drift region and has the same type of doping. The fin is tapered in the drift region, being wider closest to the undoped gate-control region and thinner closest to the drain region. A gate stack is attached to the top surface of the substrate and located with the undoped gate-control region.

Abstract translation: 具有成形漂移区域的高电压FinFET的装置和方法包括具有顶部表面的衬底和附接到顶表面的鳍的横向扩散金属氧化物半导体（LDMOS）FinFET。 散热片包括具有第一类掺杂的源极区域，与源极区域相邻的未掺杂栅极控制区域，与源极区域相对的未掺杂栅极控制区域相邻的漂移区域和漏极区域。 源极区域的掺杂量大于漂移区域中的掺杂量。 漏极区域与漂移区域相邻并且具有相同类型的掺杂。 翅片在漂移区域逐渐变细，最接近未掺杂的栅极控制区域更宽，最靠近漏极区域更薄。 栅极堆叠被附着到衬底的顶表面并且与未掺杂的栅极控制区域一起定位。

公开(公告)号：US20160380100A1

公开(公告)日：2016-12-29

申请号：US14751557

申请日：2015-06-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Andres Bryant ,  Edward J. Nowak ,  Robert R. Robison

IPC: H01L29/78 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L21/845 ,  G05F3/16 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/78696

Abstract: An integrated circuit having a reference device and method of forming the same. A reference device is disclosed having: a fully depleted n-type MOSFET implemented as a long channel device having a substantially undoped body; and a fully depleted p-type MOSFET implemented with as a long channel device having a substantially undoped body; wherein the n-type MOSFET and p-type MOSFET are connected in series and employ identical gate stacks, wherein each has a gate electrically coupled to a respective drain to form two diodes, and wherein both diodes are in one of an on state and an off state according to a value of an electrical potential applied across the n-type MOSFET and p-type MOSFET.

Abstract translation: 一种具有参考装置的集成电路及其形成方法。 公开了一种参考装置，其具有：实现为具有基本上未掺杂主体的长通道装置的完全耗尽的n型MOSFET; 以及用作具有基本上未掺杂的主体的长沟道器件实现的完全耗尽的p型MOSFET; 其中所述n型MOSFET和p型MOSFET串联连接并采用相同的栅极叠层，其中每个都具有电耦合到相应漏极的栅极以形成两个二极管，并且其中两个二极管处于导通状态和 根据施加在n型MOSFET和p型MOSFET上的电位的值的关闭状态。

公开(公告)号：US09478615B2

公开(公告)日：2016-10-25

申请号：US14493749

申请日：2014-09-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： James W. Adkisson ,  Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak

IPC: H01L29/10 ,  H01L21/28 ,  H01L29/66 ,  H01L29/08 ,  H01L29/36 ,  H01L29/78 ,  H01L21/265

CPC classification number: H01L29/1041 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/28026 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/36 ,  H01L29/66537 ,  H01L29/66583 ,  H01L29/6659 ,  H01L29/78

Abstract: A method that forms a structure implants a well implant into a substrate, patterns a mask on the substrate (to have at least one opening that exposes a channel region of the substrate) and forms a conformal dielectric layer on the mask and to line the opening. The conformal dielectric layer covers the channel region of the substrate. The method also forms a conformal gate metal layer on the conformal dielectric layer, implants a compensating implant through the conformal gate metal layer and the conformal dielectric layer into the channel region of the substrate, and forms a gate conductor on the conformal gate metal layer. Additionally, the method removes the mask to leave a gate stack on the substrate, forms sidewall spacers on the gate stack, and then forms source/drain regions in the substrate partially below the sidewall spacers.

Abstract translation: 一种形成将衬底植入衬底的结构的方法，在衬底上图案掩模（具有暴露衬底的沟道区的至少一个开口），并在掩模上形成共形电介质层并使开口 。 保形介电层覆盖衬底的沟道区。 该方法还在保形电介质层上形成共形栅极金属层，通过共形栅极金属层和共形绝缘层将补偿注入植入衬底的沟道区，并在共形栅极金属层上形成栅极导体。 此外，该方法去除掩模以在衬底上留下栅极堆叠，在栅极堆叠上形成侧壁间隔物，然后在衬底中部分地在侧壁间隔物下方形成源极/漏极区域。

公开(公告)号：US20160225680A1

公开(公告)日：2016-08-04

申请号：US14613570

申请日：2015-02-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Lyndon Ronald Logan ,  Edward J. Nowak ,  Robert R. Robison ,  Jonathan K. Winslow

IPC: H01L21/66 ,  G01R31/26 ,  H01L29/45 ,  H01L21/67 ,  H01L21/8234 ,  H01L27/118

CPC classification number: H01L22/14 ,  G01R31/2621 ,  H01L21/823431 ,  H01L22/34 ,  H01L29/45

Abstract: Various embodiments provide systems, computer program products and computer implemented methods. In some embodiments, a system includes a computer-implemented method of determining a laterally diffuse dopant profile in semiconductor structures by providing first and second semiconductor structures having plurality of gate array structures in a silicided region separated from each other by a first distance and second distance. A potential difference is applied across the plurality of gate array structures and resistances are determined. A linear-regression fit is performed on measured resistance versus the first distance and the second distance with an extrapolated x equals 0 and a y-intercept to determine a laterally diffused dopant-profile under the plurality of gate array structures based on a semiconductor device model.

Abstract translation: 各种实施例提供系统，计算机程序产品和计算机实现的方法。 在一些实施例中，系统包括计算机实现的方法，该方法通过提供具有多个栅极阵列结构的第一和第二半导体结构来确定半导体结构中的横向扩散掺杂物分布，所述第一和第二半导体结构在硅化区域中彼此分开第一距离和第二距离 。 在多个栅极阵列结构之间施加电势差，并确定电阻。 基于半导体器件模型，在测量的电阻相对于第一距离和第二距离上执行线性回归拟合，其中外推的x等于0和y截距以确定多个门阵列结构下的横向扩散的掺杂​​剂轮廓 。