公开(公告)号：US09397175B2

公开(公告)日：2016-07-19

申请号：US14881766

申请日：2015-10-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Emre Alptekin ,  Unoh Kwon ,  Wing L. Lai ,  Zhengwen Li ,  Vijay Narayanan ,  Ravikumar Ramachandran ,  Reinaldo A. Vega

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/40 ,  H01L29/51 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/49

CPC classification number: H01L29/408 ,  H01L21/82345 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659

Abstract: A first gate structure and a second gate structure are formed over a semiconductor material layer. The first gate structure includes a planar silicon-based gate dielectric, a planar high-k gate dielectric, a metallic nitride portion, and a first semiconductor material portion, and the second gate structure includes a silicon-based dielectric material portion and a second semiconductor material portion. After formation of gate spacers and a planarization dielectric layer, the second gate structure is replaced with a transient gate structure including a chemical oxide portion and a second high-k gate dielectric. A work-function metal layer and a conductive material portion can be formed in each gate electrode by replacement of semiconductor material portions. A gate electrode includes the planar silicon-based gate dielectric, the planar high-k gate dielectric, and a U-shaped high-k gate dielectric, and another gate electrode includes the chemical oxide portion and another U-shaped high-k gate dielectric.

Abstract translation: 在半导体材料层上形成第一栅极结构和第二栅极结构。 第一栅极结构包括平面硅基栅极电介质，平面高k栅极电介质，金属氮化物部分和第一半导体材料部分，并且第二栅极结构包括硅基电介质材料部分和第二半导体 材料部分。 在形成栅极间隔物和平坦化介电层之后，用包括化学氧化物部分和第二高k栅极电介质的瞬态栅极结构来代替第二栅极结构。 可以通过更换半导体材料部分在每个栅电极中形成功函数金属层和导电材料部分。 栅电极包括平面硅基栅极电介质，平面高k栅极电介质和U形高k栅极电介质，另一个栅电极包括化学氧化物部分和另一个U形高k栅极电介质 。

公开(公告)号：US09236345B2

公开(公告)日：2016-01-12

申请号：US14223592

申请日：2014-03-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Emre Alptekin ,  Nicolas L. Breil ,  Christian Lavoie ,  Ahmet S. Ozcan ,  Kathryn T. Schonenberg

IPC: H01L29/78 ,  H01L23/532 ,  H01L27/092 ,  H01L23/535 ,  H01L29/423 ,  H01L29/417 ,  H01L21/285

CPC classification number: H01L21/76886 ,  H01L21/28518 ,  H01L21/28568 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76895 ,  H01L21/823871 ,  H01L23/485 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L27/092 ,  H01L29/41766 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Contact openings are formed into a dielectric material exposing a surface portion of a semiconductor substrate. An interfacial oxide layer is then formed in each contact opening and on an exposed surface portion of the interfacial oxide layer. A NiPt alloy layer is formed within each opening and on the exposed surface portion of each interfacial oxide layer. An anneal is then performed that forms a contact structure of, from bottom to top, a nickel disilicide alloy body having an inverted pyramidal shape, a Pt rich silicide cap region and an oxygen rich region. A metal contact is then formed within each contact opening and atop the oxygen rich region of each contact structure.

Abstract translation: 接触开口形成为露出半导体衬底的表面部分的电介质材料。 然后在每个接触开口中和界面氧化物层的暴露表面部分上形成界面氧化物层。 在每个开口内和每个界面氧化物层的暴露的表面部分上形成NiPt合金层。 然后进行退火，其形成从底部到顶部具有倒金字塔形状，富Pt硅化物帽区域和富氧区域的二硅化镍合金体的接触结构。 然后在每个接触开口内和每个接触结构的富氧区顶上形成金属接触。

公开(公告)号：US20180090447A1

公开(公告)日：2018-03-29

申请号：US15826939

申请日：2017-11-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Emre Alptekin ,  Nicolas L. Breil ,  Christian Lavoie ,  Ahmet S. Ozcan ,  Kathryn T. Schonenberg

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/485 ,  H01L21/285

CPC classification number: H01L23/53266 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76879 ,  H01L21/76883 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238

Abstract: An aspect of the invention includes a method for forming a contact in a dielectric layer over a semiconductor substrate. The method may comprise: forming a contact opening in a dielectric layer over the semiconductor substrate to expose an upper portion of the semiconductor substrate; depositing a first liner layer to conformally coat the contact opening; causing a portion of the first liner layer to diffuse into the upper portion of the semiconductor substrate to form a first intermix region at the upper portion of the semiconductor substrate; depositing a refractory metal layer over the first intermix region; and depositing a metal in the contact opening thereby forming the contact.

公开(公告)号：US09647124B2

公开(公告)日：2017-05-09

申请号：US15060806

申请日：2016-03-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Emre Alptekin ,  Viraj Y. Sardesai ,  Reinaldo A. Vega

IPC: H01L29/786 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/02 ,  B82Y10/00 ,  H01L29/775 ,  H01L29/06 ,  H01L29/16 ,  H01L29/778 ,  H01L29/78

CPC classification number: H01L29/78687 ,  B82Y10/00 ,  H01L21/0237 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/02516 ,  H01L21/02527 ,  H01L21/02529 ,  H01L21/02587 ,  H01L21/02609 ,  H01L21/02664 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/1606 ,  H01L29/775 ,  H01L29/7781 ,  H01L29/7851 ,  H01L29/78696

Abstract: Semiconductor devices with graphene nanoribbons and methods of manufacture are disclosed. The method includes forming at least one layer of Si material on a substrate. The method further includes forming at least one layer of carbon based material adjacent to the at least one layer of Si. The method further includes patterning at least one of the at least one layer of Si material and the at least one layer of carbon based material. The method further includes forming graphene on the patterned carbon based material.

公开(公告)号：US20160190344A1

公开(公告)日：2016-06-30

申请号：US15060806

申请日：2016-03-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Emre Alptekin ,  Viraj Y. Sardesai ,  Reinaldo A. Vega

IPC: H01L29/786 ,  H01L29/78 ,  H01L29/16

CPC classification number: H01L29/78687 ,  B82Y10/00 ,  H01L21/0237 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/02516 ,  H01L21/02527 ,  H01L21/02529 ,  H01L21/02587 ,  H01L21/02609 ,  H01L21/02664 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0673 ,  H01L29/1606 ,  H01L29/775 ,  H01L29/7781 ,  H01L29/7851 ,  H01L29/78696

Abstract: Semiconductor devices with graphene nanoribbons and methods of manufacture are disclosed. The method includes forming at least one layer of Si material on a substrate. The method further includes forming at least one layer of carbon based material adjacent to the at least one layer of Si. The method further includes patterning at least one of the at least one layer of Si material and the at least one layer of carbon based material. The method further includes forming graphene on the patterned carbon based material.

公开(公告)号：US09368493B2

公开(公告)日：2016-06-14

申请号：US14325668

申请日：2014-07-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Emre Alptekin ,  Viraj Yashawant Sardesai ,  Cung Do Tran ,  Reinaldo Ariel Vega

IPC: H01L21/00 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/16 ,  H01L29/06 ,  H01L21/02 ,  H01L21/762 ,  H01L21/3065

CPC classification number: H01L21/76224 ,  H01L21/02115 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/02318 ,  H01L21/02378 ,  H01L21/02527 ,  H01L21/02612 ,  H01L21/02664 ,  H01L21/31116 ,  H01L21/823431 ,  H01L21/823481 ,  H01L23/3738 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/16 ,  H01L29/785

Abstract: Embodiments of the present invention provide structures and methods for heat suppression in finFET devices. Fins are formed in a semiconductor substrate. A graphene layer is formed on a lower portion of the sidewalls of the fins. A shallow trench isolation region is disposed on the structure and covers the graphene layer, while an upper portion of the fins protrudes from the shallow trench isolation region. The graphene layer may also be deposited on a top surface of the base semiconductor substrate. The graphene serves to conduct heat away from the fins more effectively than other dielectric materials.

Abstract translation: 本发明的实施例提供了finFET器件中的热抑制的结构和方法。 翅片形成在半导体衬底中。 石墨烯层形成在翅片的侧壁的下部。 浅沟槽隔离区域设置在结构上并且覆盖石墨烯层，而翅片的上部从浅沟槽隔离区域突出。 石墨烯层也可以沉积在基底半导体衬底的顶表面上。 与其它介电材料相比，石墨烯用于将散热物从翅片导出。