公开(公告)号：US20170076991A1

公开(公告)日：2017-03-16

申请号：US14853373

申请日：2015-09-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anthony I. Chou ,  Judson R. Holt ,  Arvind Kumar ,  Henry K. Utomo

IPC: H01L21/8238 ,  H01L21/266 ,  H01L27/092 ,  H01L29/78 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L21/265 ,  H01L29/08

CPC classification number: H01L21/823814 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/7848

Abstract: An aspect of the disclosure provides for an asymmetric semiconductor device. The asymmetric semiconductor device may comprise: a substrate; and a fin-shaped field effect transistor (FINFET) disposed on the substrate, the FINFET including: a set of fins disposed proximate a gate; a first epitaxial region disposed on a source region on the set of fins, the first epitaxial region having a first height; and a second epitaxial region disposed on a drain region on the set of fins, the second epitaxial region having a second height, wherein the first height is distinct from the second height.

Abstract translation: 本公开的一个方面提供了一种不对称半导体器件。 不对称半导体器件可以包括：衬底; 以及设置在所述衬底上的鳍状场效应晶体管（FINFET），所述FINFET包括：设置在栅极附近的一组翅片; 第一外延区域，设置在所述一组鳍片上的源极区域上，所述第一外延区域具有第一高度; 以及设置在所述散热片组上的漏极区域上的第二外延区域，所述第二外延区域具有第二高度，其中所述第一高度与所述第二高度不同。

公开(公告)号：US20140353741A1

公开(公告)日：2014-12-04

申请号：US13907690

申请日：2013-05-31

Applicant: STMicroelectronics, Inc. ,  GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Pietro Montanini ,  Raymond Joy ,  Marta Mottura ,  Henry K. Utomo

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66636 ,  H01L21/28123 ,  H01L21/76232 ,  H01L29/165 ,  H01L29/7848

Abstract: A method for fabricating enhanced-mobility pFET devices having channel lengths below 50 nm. Gates for pFETs may be patterned in dense arrays on a semiconductor substrate that includes shallow trench isolation (STI) structures. Partially-enclosed voids in the semiconductor substrate may be formed at source and drain regions for the gates, and subsequently filled with epitaxially-grown semiconductor that compressively stresses channel regions below the gates. Some of the gates (dummy gates) may extend over edges of the STI structures to prevent undesirable faceting of the epitaxial material in the source and drain regions.

Abstract translation: 一种制造通道长度低于50nm的增强型迁移率pFET器件的方法。 用于pFET的栅极可以在包括浅沟槽隔离（STI）结构的半导体衬底上以致密阵列图案化。 可以在用于栅极的源极和漏极区域处形成半导体衬底中的部分封闭的空隙，并且随后填充压缩地压缩栅极下方的沟道区域的外延生长的半导体。 一些栅极（伪栅极）可以在STI结构的边缘上延伸，以防止在源极和漏极区域中的外延材料的不期望的刻痕。

公开(公告)号：US10049942B2

公开(公告)日：2018-08-14

申请号：US14853373

申请日：2015-09-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anthony I. Chou ,  Judson R. Holt ,  Arvind Kumar ,  Henry K. Utomo

IPC: H01L21/265 ,  H01L21/266 ,  H01L29/167 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L27/092

Abstract: An aspect of the disclosure provides for an asymmetric semiconductor device. The asymmetric semiconductor device may comprise: a substrate; and a fin-shaped field effect transistor (FINFET) disposed on the substrate, the FINFET including: a set of fins disposed proximate a gate; a first epitaxial region disposed on a source region on the set of fins, the first epitaxial region having a first height; and a second epitaxial region disposed on a drain region on the set of fins, the second epitaxial region having a second height, wherein the first height is distinct from the second height.

公开(公告)号：US20180026137A1

公开(公告)日：2018-01-25

申请号：US15457017

申请日：2017-03-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Henry K. Utomo ,  Reinaldo A. Vega ,  Yun Y. Wang

IPC: H01L29/78

CPC classification number: H01L29/7851 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/02675 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7847 ,  H01L29/7849 ,  H01L29/785

Abstract: Device structures for a fin-type field-effect transistor (FinFET) and methods for fabricating a device structure for a FinFET. A fin comprised of a semiconductor material having a first crystal structure is formed. A dielectric layer is formed that includes an opening aligned with the fin. A dummy gate structure is removed from the opening in the dielectric layer. After the dummy gate structure is removed, a section of the fin aligned with the opening is implanted with non-dopant ions to amorphize the first crystal structure of the semiconductor material of the fin. After the section of the fin is implanted, the section of the fin is annealed such that the semiconductor material in the section of the fin recrystallizes with a second crystal structure incorporating internal strain.

公开(公告)号：US09875939B1

公开(公告)日：2018-01-23

申请号：US15373129

申请日：2016-12-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yue Ke ,  Alexander Reznicek ,  Benjamin Moser ,  Dominic J. Schepis ,  Melissa A. Smith ,  Henry K. Utomo ,  Reinaldo Vega ,  Sameer Jain

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/306 ,  H01L21/324 ,  H01L21/266 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/02532 ,  H01L21/266 ,  H01L21/30604 ,  H01L21/324 ,  H01L29/165 ,  H01L29/66795

Abstract: Methods of fabricating integrated circuit devices for forming uniform and well controlled fin recesses are disclosed. One method includes, for instance: obtaining an intermediate semiconductor structure having a substrate, at least one fin disposed on the substrate, at least one gate structure positioned over the at least one fin, and at least one oxide layer disposed on the substrate and about the at least one fin and the at least one gate structure; implanting germanium (Ge) in a first region of the at least one fin; and removing the first region of the at least one fin implanted with Ge.

公开(公告)号：US20170179257A1

公开(公告)日：2017-06-22

申请号：US15453939

申请日：2017-03-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anthony I. Chou ,  Judson R. Holt ,  Arvind Kumar ,  Henry K. Utomo

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/08 ,  H01L21/306 ,  H01L29/165 ,  H01L21/84 ,  H01L29/10

CPC classification number: H01L29/66636 ,  H01L21/30604 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66742 ,  H01L29/78 ,  H01L29/7848 ,  H01L29/786

Abstract: The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a partially depleted semiconductor-on-insulator (SOI) junction isolation structure using a nonuniform trench shape formed by reactive ion etching (RIE) and crystallographic wet etching. The nonuniform trench shape may reduce back channel leakage by providing an effective channel directly below a gate stack having a width that is less than a width of an effective back channel directly above the isolation layer.

公开(公告)号：US09634084B1

公开(公告)日：2017-04-25

申请号：US15040477

申请日：2016-02-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Christopher D. Sheraw ,  Chengwen Pei ,  Eric T. Harley ,  Yue Ke ,  Henry K. Utomo ,  Yinxiao Yang ,  Zhibin Ren

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/324 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L29/0615 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/324 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785

Abstract: Fin-type transistor fabrication methods and structures are provided which include, for example, providing a gate structure extending at least partially over a fin extended above a substrate structure, the gate structure being disposed adjacent to at least one region of the fin; disposing a protective film conformally over the gate structure and over the at least one region; modifying the protective film over the at least one region of the fin to form a conformal buffer layer, wherein the modifying selectively alters a crystalline structure of the protective film over the at least one region which thereby becomes the conformal buffer layer, without altering the crystalline structure of the protective film disposed over the gate structure; and removing the un-altered protective film over the gate structure, leaving the conformal buffer layer over the at least one region to form a source region and a drain region of the fin-type transistor.

公开(公告)号：US09577099B2

公开(公告)日：2017-02-21

申请号：US14641917

申请日：2015-03-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Veeraraghavan S. Basker ,  Eric C. T. Harley ,  Yue Ke ,  Alexander Reznicek ,  Henry K. Utomo

IPC: H01L29/00 ,  H01L21/00 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/04 ,  H01L29/45 ,  H01L21/306

CPC classification number: H01L29/785 ,  H01L21/30604 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor structure includes a fin upon a semiconductor substrate. A clean epitaxial growth surface is provided by forming a buffer layer upon fin sidewalls and an upper surface of the fin. The buffer layer may be epitaxially grown. Diamond shaped epitaxy is grown from the buffer layer sidewalls. In some implementations, the diamond shaped epitaxy may be subsequently merged with surrounding dielectric. A dopant concentration of the surrounding dielectric may be higher than a dopant concentration of the diamond shaped epitaxy.

Abstract translation: 半导体结构包括半导体衬底上的翅片。 通过在翅片侧壁和翅片的上表面上形成缓冲层来提供干净的外延生长表面。 缓冲层可以外延生长。 菱形外延从缓冲层侧壁生长。 在一些实施方案中，钻石形外延可以随后与周围的电介质合并。 周围电介质的掺杂剂浓度可高于菱形外延的掺杂剂浓度。