中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

28 records (took 0.013 seconds)

    Sensing circuits for charge trap transistors
    14.
    发明授权
    Sensing circuits for charge trap transistors 有权

    公开(公告)号：US11101010B2

    公开(公告)日：2021-08-24

    申请号：US16568394

    申请日：2019-09-12

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Eric D. Hunt-Schroeder ,  Sebastian T. Ventrone ,  James A. Svarczkopf ,  Igor Arsovski

    IPC: G11C17/18 ,  G11C7/06 ,  G11C7/08 ,  G11C11/409

    Abstract: The present disclosure relates to a structure including a first delay path circuit which is configured to receive an input signal and is connected to a complement transistor of a twin cell transistor pair through a complement bitline signal, a second delay path circuit which is configured to receive the input signal and is connected to a true transistor of the twin cell transistor pair through a true bitline signal, and a logic circuit which is configured to receive a first output of the first delay path circuit and a second output of the second delay path circuit and output a data output signal.

    CONTENT-ADDRESSABLE MEMORY HAVING MULTIPLE REFERENCE MATCHLINES TO REDUCE LATENCY
    16.
    发明申请
    CONTENT-ADDRESSABLE MEMORY HAVING MULTIPLE REFERENCE MATCHLINES TO REDUCE LATENCY 有权

    公开(公告)号：US20170200500A1

    公开(公告)日：2017-07-13

    申请号：US14990125

    申请日：2016-01-07

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Igor Arsovski ,  Michael T. Fragano ,  Robert M. Houle ,  Thomas M. Maffitt

    IPC: G11C15/04

    CPC classification number: G11C15/04

    Abstract: Words of data are maintained in content-addressable memory cells arranged in rows. Two of the rows are timing reference rows, and the remainder of the rows are data rows that maintain the words of data. The data rows form individual matchlines. A first of the reference rows forms a precharge reference matchline, and a second of the reference rows forms an evaluation reference matchline. The timing for the individual matchlines to precharge is based on the time to precharge the precharge reference matchline, and timing for the individual matchlines to evaluate a search word is based on the time for the evaluation reference matchline to evaluate the search word.

    Matchline precharge architecture for self-reference matchline sensing
    17.
    发明授权
    Matchline precharge architecture for self-reference matchline sensing 有权
    匹配线预充电结构，用于自参考匹配线感测

    公开(公告)号：US09583192B1

    公开(公告)日：2017-02-28

    申请号：US15164325

    申请日：2016-05-25

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Igor Arsovski ,  Michael T. Fragano ,  Thomas M. Maffitt ,  Robert M. Houle

    IPC: G11C15/04 ,  G11C15/00 ,  G11C7/08 ,  G11C7/12

    CPC classification number: G11C15/04 ,  G11C7/08 ,  G11C7/12 ,  G11C15/00

    Abstract: The present disclosure relates to content addressable memories (CAM), and more particularly, to a searchable CAM structure having self-reference matchline precharge and local feedback control and method of use. The present disclosure includes a structure which includes: a sense line connected to a sensing device; a feedback line connected to the sense line at a tap point between a first end and a second end of the sense line; and a local precharge controller connected to the tap point by the feedback line to control precharging of the sense line according to a state of the feedback line.

    Abstract translation: 本公开涉及内容可寻址存储器（CAM），更具体地，涉及具有自参考匹配线预充电和本地反馈控制以及使用方法的可搜索CAM结构。 本公开包括：结构，其包括：感测线，连接到感测装置; 在感测线的第一端和第二端之间的抽头点处连接到感测线的反馈线; 以及通过反馈线连接到分接点的局部预充电控制器，以根据反馈线的状态控制感测线的预充电。

    Self pre-charging memory circuits
    18.
    发明授权
    Self pre-charging memory circuits 有权

    公开(公告)号：US09886998B2

    公开(公告)日：2018-02-06

    申请号：US15175466

    申请日：2016-06-07

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Igor Arsovski ,  Qing Li ,  Wei Zhao ,  Xiaoli Hu

    IPC: G11C11/419

    CPC classification number: G11C11/419 ,  G11C7/067

    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to sensing circuit for a memory and methods of use. The memory includes a self-referenced sense amp that is structured to calibrate its individual pre-charge based on a trip-point, with autonomous pre-charge activation circuitry that starts pre-charging a sense-line on each unique entry as soon as a sense has been performed or completed.

    DOUBLE BANDWIDTH ALGORITHMIC MEMORY ARRAY
    20.
    发明申请
    DOUBLE BANDWIDTH ALGORITHMIC MEMORY ARRAY 有权

    公开(公告)号：US20170315738A1

    公开(公告)日：2017-11-02

    申请号：US15140016

    申请日：2016-04-27

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Igor Arsovski ,  Eric D. Hunt-Schroeder ,  Mark W. Kuemerle

    IPC: G06F3/06

    CPC classification number: G06F11/108

    Abstract: The present disclosure relates to memory structures and, more particularly, to double bandwidth algorithmic memory array structures and methods of use. The memory array includes: a plurality of memory banks each of which includes addressable storage units; a redundant array of independent disks (RAID) bank which stores parity bits corresponding to data written into any of the plurality of memory banks at a same address; and a plurality of XOR gates in which data written into any of the plurality of memory banks is cascaded therethrough to refresh the parity bits in the RAID bank.

Patent Agency Ranking