公开(公告)号：US20150348849A1

公开(公告)日：2015-12-03

申请号：US14294467

申请日：2014-06-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Jan Hoentschel ,  Gerd Zschaetzsch

IPC: H01L21/8238 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66 ,  H01L21/265 ,  H01L21/762 ,  H01L29/06 ,  H01L29/45 ,  H01L21/285 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L21/823814 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76879 ,  H01L21/823412 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/456 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method of forming a transistor device is provided, including the subsequently performed steps of forming a gate electrode on a first semiconductor layer, forming an interlayer dielectric over the gate electrode and the first semiconductor layer, forming a first opening in the interlayer dielectric at a predetermined distance laterally spaced from the gate electrode on one side of the gate electrode and a second opening in the interlayer dielectric at a predetermined distance laterally spaced from the gate electrode on another side of the gate electrode, the first and second openings reaching to the first semiconductor layer, forming cavities in the first semiconductor layer through the first and second openings formed in the interlayer dielectric, and forming embedded second semiconductor layers in the cavities.

Abstract translation: 提供了一种形成晶体管器件的方法，包括随后执行的步骤，在第一半导体层上形成栅电极，在栅电极和第一半导体层上形成层间电介质，在层间电介质中形成第一开口 在栅电极的一侧上与栅电极横向间隔开的预定距离，并且在栅极电极的另一侧与栅电极横向间隔开预定距离的层间电介质中的第二开口，第一和第二开口到达第一 半导体层，通过形成在层间电介质中的第一和第二开口在第一半导体层中形成空腔，以及在空腔中形成嵌入的第二半导体层。

公开(公告)号：US09035306B2

公开(公告)日：2015-05-19

申请号：US13869162

申请日：2013-04-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jan Hoentschel ,  Robert Mulfinger ,  Vassilios Papageorgiou

IPC: H01L23/58 ,  H01L21/84 ,  H01L27/12 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L23/58 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a sophisticated semiconductor device, FINFET elements may be provided with individually accessible semiconductor fins which may be connected to a controllable interconnect structure for appropriately adjusting the transistor configuration, for instance with respect to current drive capability, replacing defective semiconductor fins and the like. Consequently, different transistor configurations may be obtained on the basis of a standard transistor cell architecture, which may result in increased production yield of highly complex manufacturing strategies in forming non-planar transistor devices.

Abstract translation: 在复杂的半导体器件中，FINFET元件可以设置有单独可访问的半导体鳍片，其可以连接到可控制的互连结构，以适当地调整晶体管配置，例如关于电流驱动能力，替换有缺陷的半导体鳍片等。 因此，可以在标准晶体管单元架构的基础上获得不同的晶体管配置，这可能导致在形成非平面晶体管器件时高度复杂的制造策略的生产成本增加。

公开(公告)号：US09012956B2

公开(公告)日：2015-04-21

申请号：US13783517

申请日：2013-03-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Ralf Richter ,  Jan Hoentschel

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238

CPC classification number: H01L21/823418 ,  H01L21/28518 ,  H01L21/823412 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/401 ,  H01L29/41766 ,  H01L29/66431 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

Abstract: When forming sophisticated P-channel transistors, a semiconductor alloy layer is formed on the surface of the semiconductor layer including the transistor active region. When a metal silicide layer is formed contiguous to this semiconductor alloy layer, an agglomeration of the metal silicide layer into isolated clusters is observed. In order to solve this problem, the present invention proposes a method and a semiconductor device wherein the portion of the semiconductor alloy layer lying on the source and drain regions of the transistor is removed before formation of the metal silicide layer is performed. In this manner, the metal silicide layer is formed so as to be contiguous to the semiconductor layer, and not to the semiconductor alloy layer.

Abstract translation: 当形成复杂的P沟道晶体管时，在包括晶体管有源区的半导体层的表面上形成半导体合金层。 当与该半导体合金层邻接形成金属硅化物层时，观察到金属硅化物层与分离的团簇的聚集。 为了解决这个问题，本发明提出一种方法和半导体器件，其中在形成金属硅化物层之前去除位于晶体管的源极和漏极区域上的半导体合金层的部分。 以这种方式，金属硅化物层形成为与半导体层邻接，而不形成为半导体合金层。

公开(公告)号：US20150076618A1

公开(公告)日：2015-03-19

申请号：US14031361

申请日：2013-09-19

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ran Yan ,  Nicolas Sassiat ,  Ralf Richter ,  Jan Hoentschel

IPC: H01L29/423 ,  H01L29/10 ,  H01L29/40

CPC classification number: H01L29/42376 ,  H01L29/1037 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/7854

Abstract: Methods and apparatus are provided for an integrated circuit. The method includes forming a corrugation mask on a substrate, and forming a channel corrugation on the substrate. The corrugation mask is removed from the substrate, and a gate insulator is formed overlying the channel corrugation on the substrate. A gate is formed overlying the channel gate insulator.

Abstract translation: 为集成电路提供了方法和装置。 该方法包括在衬底上形成波纹掩模，并在衬底上形成通道波纹。 将波纹掩模从基板上移除，并且在衬底上形成覆盖通道波纹的栅极绝缘体。 栅极形成在通道栅极绝缘体上方。

公开(公告)号：US08963208B2

公开(公告)日：2015-02-24

申请号：US13678054

申请日：2012-11-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Matthias Kessler ,  Jan Hoentschel

IPC: H01L21/00 ,  H01L21/02 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/762 ,  H01L29/66 ,  H01L27/12 ,  H01L27/06 ,  H01L29/94 ,  H01L27/088

CPC classification number: H01L21/84 ,  H01L21/02428 ,  H01L21/76283 ,  H01L21/823412 ,  H01L21/823878 ,  H01L27/0629 ,  H01L27/088 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/20 ,  H01L29/66181 ,  H01L29/7786 ,  H01L29/78 ,  H01L29/861 ,  H01L29/945

Abstract: A structure comprises a semiconductor substrate, a semiconductor-on-insulator region and a bulk region. The semiconductor-on-insulator region comprises a first semiconductor region, a dielectric layer provided between the semiconductor substrate and the first semiconductor region, and a first transistor comprising an active region provided in the first semiconductor region. The dielectric layer provides electrical isolation between the first semiconductor region and the semiconductor substrate. The bulk region comprises a second semiconductor region provided directly on the semiconductor substrate.

公开(公告)号：US08951877B2

公开(公告)日：2015-02-10

申请号：US13799741

申请日：2013-03-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nicolas Sassiat ,  Carsten Grass ,  Jan Hoentschel ,  Ran Yan ,  Ralf Richter

IPC: H01L21/336 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/78642 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/6675

Abstract: When forming cavities in active regions of semiconductor devices in order to incorporate a strain-inducing semiconductor material, an improved shape of the cavities may be achieved by using an amorphization process and a heat treatment so as to selectively modify the etch behavior of exposed portions of the active regions and to adjust the shape of the amorphous regions. In this manner, the basic configuration of the cavities may be adjusted with a high degree of flexibility. Consequently, the efficiency of the strain-inducing technique may be improved.

Abstract translation: 当在半导体器件的有源区域中形成空腔以引入应变诱导半导体材料时，可以通过使用非晶化过程和热处理来实现空腔的改进形状，以便选择性地改变暴露部分的蚀刻行为 活性区域并调整非晶区域的形状。 以这种方式，可以以高度的灵活性来调节空腔的基本构造。 因此，可以提高应变诱导技术的效率。

公开(公告)号：US20140361385A1

公开(公告)日：2014-12-11

申请号：US13911857

申请日：2013-06-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alban Zaka ,  Ran Yan ,  Nicolas Sassiat ,  El Mehdi Bazizi ,  Jan Hoentschel

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L21/265 ,  H01L21/2658 ,  H01L21/28176 ,  H01L29/4916 ,  H01L29/51 ,  H01L29/6659 ,  H01L29/7833

Abstract: Methods of forming a semiconductor device structure at advanced technology nodes and respective semiconductor device structures are provided at advanced technology nodes, i.e., smaller than 100 nm. In some illustrative embodiments, a fluorine implantation process for implanting fluorine at least into a polysilicon layer formed over a dielectric layer structure is performed prior to patterning the gate dielectric layer structure and the polysilicon layer for forming a gate structure and implanting source and drain regions at opposing sides of the gate structure.

Abstract translation: 在先进技术节点上形成半导体器件结构的方法和相应的半导体器件结构在低于100nm的技术节点上提供。 在一些说明性实施例中，在将栅极电介质层结构和用于形成栅极结构的多晶硅层图案化并且将源极和漏极区域注入到其中之前，至少将至少注入形成在电介质层结构上的多晶硅层中的氟注入工艺 门结构的两侧。

公开(公告)号：US20140357042A1

公开(公告)日：2014-12-04

申请号：US13907362

申请日：2013-05-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ralf Richter ,  Stefan Flachowsky ,  Jan Hoentschel

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/266

CPC classification number: H01L29/6653 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/28008 ,  H01L21/823864 ,  H01L29/4966 ,  H01L29/4983 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/6659 ,  H01L29/7833

Abstract: A known problem when manufacturing transistors is the stress undesirably introduced by the spacers into the transistor channel region. In order to solve this problem, the present invention proposes an ion implantation aimed at relaxing the stress of the spacer materials. The relax implantation is performed after the spacer has been completely formed. The relax implantation may be performed after a silicidation process or after an implantation step in the source and drain regions followed by an activation annealing and before performing the silicidation process.

Abstract translation: 制造晶体管时的已知问题是由间隔物不期望地引入晶体管沟道区域的应力。 为了解决这个问题，本发明提出了一种旨在缓和间隔物材料的应力的离子注入。 在间隔件已经完全形成之后进行松弛植入。 松弛植入可以在硅化处理之后或在源极和漏极区域中的注入步骤之后进行激活退火并且在进行硅化处理之前进行。

公开(公告)号：US20140319620A1

公开(公告)日：2014-10-30

申请号：US13874200

申请日：2013-04-30

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Jan Hoentschel ,  Stefan Flachowsky ,  Nicolas Sassiat ,  Ralf Richter

IPC: H01L49/02 ,  H01L21/8234 ,  H01L27/06

CPC classification number: H01L28/20 ,  H01L27/0629 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66606 ,  H01L29/78

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, an integrated circuit includes a first transistor structure that includes an etch-stop material layer, a first workfunction material layer disposed over the etch-stop material layer, a second workfunction material layer disposed over the first workfunction material layer, and a metal fill material disposed over the second workfunction material layer. The integrated circuit further includes a second transistor structure that includes a layer of the etch-stop material, a layer of the second workfunction material disposed over the etch-stop material layer, and a layer of the metal fill material disposed over the second workfunction material layer. Still further, the integrated circuit includes a resistor structure that includes a layer of the etch-stop material, a layer of the metal fill material disposed over the etch-stop material layer, and a silicon material layer disposed over the metal fill material layer.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在一个实施例中，集成电路包括第一晶体管结构，其包括蚀刻停止材料层，设置在蚀刻停止材料层上的第一功函数材料层，设置在第一功函数材料层上的第二功函数材料层，以及 设置在第二功函数材料层上的金属填充材料。 集成电路还包括第二晶体管结构，其包括蚀刻停止材料层，设置在蚀刻停止材料层上的第二功函件层，以及设置在第二功函数材料上的金属填充材料层 层。 此外，集成电路包括电阻器结构，其包括蚀刻停止材料层，设置在蚀刻停止材料层上的金属填充材料层以及设置在金属填充材料层上的硅材料层。

公开(公告)号：US20140256137A1

公开(公告)日：2014-09-11

申请号：US13793082

申请日：2013-03-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ralf Richter ,  Jan Hoentschel ,  Sven Beyer ,  Peter Javorka

IPC: H01L21/265

CPC classification number: H01L21/265 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/31155 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/7843

Abstract: A method includes providing a semiconductor structure including a substrate and a transistor element. A layer of a spacer material is deposited over the substrate and the gate structure, wherein the deposited layer of spacer material has an intrinsic stress. Ions are implanted into the layer of spacer material. After the deposition of the layer of spacer material and the implantation of ions into the layer of spacer material, a sidewall spacer is formed at sidewalls of the gate structure from the layer of spacer material.

Abstract translation: 一种方法包括提供包括衬底和晶体管元件的半导体结构。 在衬底和栅极结构上沉积间隔材料层，其中间隔物材料的沉积层具有固有应力。 离子被植入到间隔物材料层中。 在间隔物材料层沉积并将离子注入到间隔物材料层中之后，在间隔物材料层的栅极结构的侧壁处形成侧壁间隔物。