公开(公告)号：US20150064812A1

公开(公告)日：2015-03-05

申请号：US14012563

申请日：2013-08-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Joachim Patzer ,  Ardechir Pakfar ,  Dominic Thurmer ,  Chih-Chun Wang ,  Remi Riviere ,  Robert Melzer ,  Bastian Haussdoerfer ,  Martin Weisheit

IPC: H01L21/311 ,  H01L21/66

CPC classification number: H01L22/12 ,  H01L21/31058 ,  H01L21/31144 ,  H01L21/823828 ,  H01L21/823878 ,  H01L22/20 ,  H01L27/0629

Abstract: A method for the manufacture of a semiconductor device is provided, including the steps of providing a semiconductor substrate including a first area separated from a second area by a first isolation region, wherein the second area includes an intermediate transistor comprising a gate electrode, forming an oxide layer over the first and second areas, forming an organic planarization layer (OPL) over the oxide layer, forming a mask layer over the OPL in the first area without covering the OPL in the second area, and etching the OPL with the mask layer being present to expose the oxide layer over the gate electrode of the transistor.

Abstract translation: 提供了一种用于制造半导体器件的方法，包括以下步骤：提供包括由第一隔离区域与第二区域分离的第一区域的半导体衬底，其中第二区域包括包括栅电极的中间晶体管，形成 在所述第一区域和所述第二区域上形成氧化物层，在所述氧化物层上形成有机平坦化层（OPL），在所述第一区域中的OPL上形成掩模层，而不覆盖所述第二区域中的所述OPL，并且用所述掩模层 存在以将氧化物层暴露在晶体管的栅电极之上。

公开(公告)号：US08906794B1

公开(公告)日：2014-12-09

申请号：US13956844

申请日：2013-08-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Joachim Patzer ,  Ardechir Pakfar ,  Clemens Fitz ,  Dominic Thurmer

IPC: H01L21/00 ,  H01L27/088 ,  H01L21/28

CPC classification number: H01L21/823443 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/32053 ,  H01L21/321 ,  H01L21/324 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/4925 ,  H01L29/4933

Abstract: A method for performing silicidation of gate electrodes includes providing a semiconductor device having first and second transistors with first and second gate electrodes formed on a semiconductor substrate, forming an oxide layer on the first and second gate electrodes and the semiconductor substrate, forming a cover layer on the oxide layer, and back etching the cover layer to expose portions of the oxide layer above the first and second gate electrodes while maintaining a portion of the cover layer between the first and second gate electrodes. Furthermore, the exposed portions of the oxide layer are removed from the first and second gate electrodes to expose upper portions of the first and second gate electrodes, while maintaining a portion of the oxide layer between the first and second gate electrodes, and a silicidation of the exposed upper portions of the first and second gate electrodes is performed.

Abstract translation: 一种用于执行栅电极的硅化的方法包括提供具有第一和第二晶体管的半导体器件，其中第一和第二栅电极形成在半导体衬底上，在第一和第二栅电极和半导体衬底上形成氧化物层，形成覆盖层 在所述氧化物层上，并且背面蚀刻所述覆盖层以暴露所述第一和第二栅电极之上的所述氧化物层的部分，同时保持所述覆盖层的所述第一和第二栅电极之间的一部分。 此外，从第一和第二栅电极去除氧化层的暴露部分，以暴露第一和第二栅电极的上部，同时保持第一和第二栅电极之间的氧化物层的一部分，以及硅化 执行第一和第二栅电极的暴露的上部。

公开(公告)号：US08889022B2

公开(公告)日：2014-11-18

申请号：US13781874

申请日：2013-03-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hans-Peter Moll ,  Joachim Patzer

IPC: B44C1/22 ,  H01L21/02

CPC classification number: H01L21/02107 ,  H01L21/32105 ,  H01L21/32134 ,  H01L21/32137 ,  H01L21/32155 ,  H01L21/823468 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/66659

Abstract: One illustrative method disclosed herein includes forming a structure above a semiconductor substrate, performing a conformal deposition process to form a layer of undoped spacer material above the structure, performing an angled ion implant process to form a region of doped spacer material in the layer of undoped spacer material while leaving other portions of the layer of undoped spacer material undoped, and, after performing the angled ion implant process, performing at least one etching process that removes the undoped portions of the layer of undoped spacer material and thereby results in a sidewall spacer comprised of the doped spacer material positioned adjacent at least one side, but not all sides, of the structure.

Abstract translation: 本文公开的一种示例性方法包括在半导体衬底上形成结构，执行保形沉积工艺以在结构上方形成未掺杂的间隔物材料层，执行成角度的离子注入工艺以在未掺杂的层中形成掺杂间隔物材料的区域 间隔材料，同时留下未掺杂的未掺杂的间隔物材料层的其它部分，并且在执行成角度离子注入工艺之后，执行至少一个蚀刻工艺，其去除未掺杂间隔物材料层的未掺杂部分，从而导致侧壁间隔物 包括位于该结构的至少一侧但不是全部侧面的掺杂间隔物材料。

公开(公告)号：US09177871B2

公开(公告)日：2015-11-03

申请号：US14143362

申请日：2013-12-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Joachim Patzer ,  Peter Baars ,  Bastian Haussdoerfer

IPC: H01L21/8238 ,  H01L21/285 ,  H01L21/265 ,  H01L21/311

CPC classification number: H01L21/823864 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/28518 ,  H01L21/31144 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/665 ,  H01L29/7848

Abstract: An issue arises when manufacturing semiconductor circuits including PFETs with an SiGe alloy embedded in their source/drain regions and NFETs without any embedded SiGe alloy. In this case, the thickness of the NFET spacers is considerably greater than that of the PFET spacers. In order to alleviate this asymmetry in spacer thickness, a manufacturing flow is proposed wherein a spacer-reducing etching process is introduced before the salicidation. The etching process is performed directly after the ion implantation performed in order to form deep regions of source/drain regions of the NFETs. Thus, the spacer-reducing etching process may be performed in the presence of the same mask used during the NFET deep implantations. The spacer-reducing etching process results in thinning of the NFET spacer structures, thus alleviating the spacer thickness imbalance between NFETs and PFETs.

Abstract translation: 当制造半导体电路时，包括在其源极/漏极区域中嵌入SiGe合金的PFET和没有任何嵌入的SiGe合金的NFET的半导体电路。 在这种情况下，NFET间隔物的厚度明显大于PFET间隔物的厚度。 为了减轻间隔物厚度的这种不对称性，提出了在盐水化之前引入间隔物减少蚀刻工艺的制造流程。 在进行离子注入之后，直接进行蚀刻处理，以形成NFET的源/漏区的深区域。 因此，间隔物减少蚀刻工艺可以在NFET深度注入期间使用的相同掩模的存在下进行。 间隔物减少蚀刻工艺导致NFET间隔物结构的变薄，从而减轻NFET和PFET之间的间隔物厚度不平衡。

公开(公告)号：US09034746B2

公开(公告)日：2015-05-19

申请号：US14524023

申请日：2014-10-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Joachim Patzer ,  Ardechir Pakfar ,  Clemens Fitz ,  Dominic Thurmer

IPC: H01L21/02 ,  H01L21/8234 ,  H01L29/49 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/324 ,  H01L21/28

CPC classification number: H01L21/823443 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/32053 ,  H01L21/321 ,  H01L21/324 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/4925 ,  H01L29/4933

Abstract: A method for performing silicidation of gate electrodes includes providing a semiconductor device having first and second transistors with first and second gate electrodes formed on a semiconductor substrate, forming an oxide layer on the first and second gate electrodes and the semiconductor substrate, forming a cover layer on the oxide layer, and back etching the cover layer to expose portions of the oxide layer above the first and second gate electrodes while maintaining a portion of the cover layer between the first and second gate electrodes. Furthermore, the exposed portions of the oxide layer are removed from the first and second gate electrodes to expose upper portions of the first and second gate electrodes, while maintaining a portion of the oxide layer between the first and second gate electrodes, and a silicidation of the exposed upper portions of the first and second gate electrodes is performed.

Abstract translation: 一种用于执行栅电极的硅化的方法包括提供具有第一和第二晶体管的半导体器件，其中第一和第二栅电极形成在半导体衬底上，在第一和第二栅电极和半导体衬底上形成氧化物层，形成覆盖层 在所述氧化物层上，并且背面蚀刻所述覆盖层以暴露所述第一和第二栅电极之上的所述氧化物层的部分，同时保持所述覆盖层的所述第一和第二栅电极之间的一部分。 此外，从第一和第二栅电极去除氧化层的暴露部分，以暴露第一和第二栅电极的上部，同时保持第一和第二栅电极之间的氧化物层的一部分，以及硅化 执行第一和第二栅极的暴露的上部。

公开(公告)号：US20150084183A1

公开(公告)日：2015-03-26

申请号：US14033789

申请日：2013-09-23

Applicant: Globalfoundries, Inc.

Inventor： Joachim Patzer ,  Hans-Peter Moll

IPC: H01L21/033 ,  H01L21/768

CPC classification number: H01L21/0332 ,  H01L21/28512 ,  H01L21/76886 ,  H01L27/0629 ,  H01L28/20

Abstract: Methods and apparatus are provided for an integrated circuit with a transistor and a resistor. The method includes depositing a first dielectric layer over the transistor and the resistor, followed by an amorphous silicon layer. The amorphous silicon layer is implanted over the resistor to produce an etch mask, and the amorphous silicon layer and first dielectric layer are removed over the transistor. A contact location on the transistor is then silicided.

Abstract translation: 为具有晶体管和电阻器的集成电路提供了方法和装置。 该方法包括在晶体管和电阻器之上沉积第一介电层，随后是非晶硅层。 将非晶硅层注入电阻器上以产生蚀刻掩模，并且在晶体管上去除非晶硅层和第一介电层。 然后将晶体管上的接触位置硅化。

公开(公告)号：US20150044861A1

公开(公告)日：2015-02-12

申请号：US14524023

申请日：2014-10-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Joachim Patzer ,  Ardechir Pakfar ,  Clemens Fitz ,  Dominic Thurmer

IPC: H01L21/8234 ,  H01L21/28 ,  H01L21/321 ,  H01L21/324 ,  H01L29/49 ,  H01L21/3205

CPC classification number: H01L21/823443 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/32053 ,  H01L21/321 ,  H01L21/324 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/4925 ,  H01L29/4933

Abstract: A method for performing silicidation of gate electrodes includes providing a semiconductor device having first and second transistors with first and second gate electrodes formed on a semiconductor substrate, forming an oxide layer on the first and second gate electrodes and the semiconductor substrate, forming a cover layer on the oxide layer, and back etching the cover layer to expose portions of the oxide layer above the first and second gate electrodes while maintaining a portion of the cover layer between the first and second gate electrodes. Furthermore, the exposed portions of the oxide layer are removed from the first and second gate electrodes to expose upper portions of the first and second gate electrodes, while maintaining a portion of the oxide layer between the first and second gate electrodes, and a silicidation of the exposed upper portions of the first and second gate electrodes is performed.

Abstract translation: 一种用于执行栅电极的硅化的方法包括提供具有第一和第二晶体管的半导体器件，其中第一和第二栅电极形成在半导体衬底上，在第一和第二栅电极和半导体衬底上形成氧化物层，形成覆盖层 在所述氧化物层上，并且背面蚀刻所述覆盖层以暴露所述第一和第二栅电极之上的所述氧化物层的部分，同时保持所述覆盖层的所述第一和第二栅电极之间的一部分。 此外，从第一和第二栅电极去除氧化层的暴露部分，以暴露第一和第二栅电极的上部，同时保持第一和第二栅电极之间的氧化物层的一部分，以及硅化 执行第一和第二栅电极的暴露的上部。