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    Methods of reducing material loss in isolation structures by introducing inert atoms into oxide hard mask layer used in growing channel semiconductor material
    11.
    发明授权
    Methods of reducing material loss in isolation structures by introducing inert atoms into oxide hard mask layer used in growing channel semiconductor material 有权
    通过将惰性原子引入用于生长通道半导体材料中的氧化物硬掩模层中来减少隔离结构中的材料损失的方法

    公开(公告)号：US08871586B2

    公开(公告)日：2014-10-28

    申请号：US13654849

    申请日：2012-10-18

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Thilo Scheiper ,  Jan Hoentschel ,  Markus Lenski ,  Rolf Stephan

    IPC: H01L21/8234

    CPC classification number: H01L21/823878 ,  H01L21/76224 ,  H01L21/823807 ,  Y02P80/30

    Abstract: In one example, the method includes forming a plurality of isolation structures in a semiconducting substrate that define first and second active regions where first and second transistor devices, respectively, will be formed, forming a hard mask layer on a surface of the substrate above the first and second active regions, wherein the hard mask layer comprises at least one of carbon, fluorine, xenon or germanium ions, performing a first etching process to remove a portion of the hard mask layer and expose a surface of one of the first and second active regions, after performing the first etching process, forming a channel semiconductor material on the surface of the active region that was exposed by the first etching process, and after forming the channel semiconductor material, performing a second etching process to remove remaining portions of the hard mask layer that were not removed during the first etching process.

    Abstract translation: 在一个示例中，该方法包括在半导体衬底中形成多个隔离结构，其限定第一和第二有源区，其中将分别形成第一和第二晶体管器件，在衬底的表面上形成硬掩模层， 第一和第二有源区，其中所述硬掩模层包括碳，氟，氙或锗离子中的至少一种，执行第一蚀刻工艺以去除所述硬掩模层的一部分并暴露所述第一和第二有源区中的一个的表面 活性区域，在进行第一蚀刻工艺之后，在通过第一蚀刻工艺曝光的有源区的表面上形成沟道半导体材料，并且在形成沟道半导体材料之后，执行第二蚀刻工艺以除去 硬掩模层，其在第一蚀刻工艺期间未被除去。

    Work function adjustment in high-K metal gate electrode structures by selectively removing a barrier layer
    14.
    发明授权
    Work function adjustment in high-K metal gate electrode structures by selectively removing a barrier layer 有权
    通过选择性去除阻挡层，在高K金属栅电极结构中进行功函数调整

    公开(公告)号：US08440559B2

    公开(公告)日：2013-05-14

    申请号：US13624235

    申请日：2012-09-21

    Applicant: Globalfoundries Inc.

    Inventor： Markus Lenski ,  Klaus Hempel ,  Vivien Schroeder ,  Robert Binder ,  Joachim Metzger

    IPC: H01L21/8234

    CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/82345 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

    Abstract: Generally, the present disclosure is directed work function adjustment in high-k metal gate electrode structures. In one illustrative embodiment, a method is disclosed that includes removing a placeholder material of a first gate electrode structure and a second gate electrode structure, and forming a first work function adjusting material layer in the first and second gate electrode structures, wherein the first work function adjusting material layer includes a tantalum nitride layer. The method further includes removing a portion of the first work function adjusting material layer from the second gate electrode structure by using the tantalum nitride layer as an etch stop layer, removing the tantalum nitride layer by performing a wet chemical etch process, and forming a second work function adjusting material layer in the second gate electrode structure and above a non-removed portion of the first work function adjusting material layer in the first gate electrode structure.

    Abstract translation: 通常，本公开涉及高k金属栅电极结构中的功函数调整。 在一个说明性实施例中，公开了一种方法，其包括移除第一栅极电极结构和第二栅电极结构的占位符材料，以及在第一和第二栅电极结构中形成第一功函数调节材料层，其中第一工件 功能调整材料层包括氮化钽层。 该方法还包括通过使用氮化钽层作为蚀刻停止层从第二栅极电极结构去除第一功函数调整材料层的一部分，通过执行湿化学蚀刻工艺去除氮化钽层，以及形成第二 第二栅电极结构中的功函数调整材料层，以及第一栅电极结构中的第一功函数调整材料层的未除去部分之上。

    METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH ROBUST GATE ELECTRODE STRUCTURE PROTECTION
    15.
    发明申请
    METHODS FOR FABRICATING INTEGRATED CIRCUITS WITH ROBUST GATE ELECTRODE STRUCTURE PROTECTION 有权
    用坚固的门电极结构保护制造集成电路的方法

    公开(公告)号：US20150132914A1

    公开(公告)日：2015-05-14

    申请号：US14080558

    申请日：2013-11-14

    Applicant: GLOBALFOUNDRIES, Inc.

    Inventor： Joanna Wasyluk ,  Dominic Thurmer ,  Ardechir Pakfar ,  Markus Lenski

    IPC: H01L29/66

    CPC classification number: H01L29/6656 ,  H01L29/165 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636

    Abstract: Methods for fabricating an integrated circuit are provided herein. In an embodiment, a method for fabricating an integrated circuit includes forming a gate electrode structure overlying a semiconductor substrate. First sidewall spacers are formed adjacent to sidewalls of the gate electrode structure, and the first sidewall spacers include a nitride. An oxide etchant is applied to a surface of the semiconductor substrate after forming the first sidewall spacers. A second spacer material that includes a nitride is deposited over the semiconductor substrate and the first sidewall spacers to form a second spacer layer after applying the oxide etchant to the surface of the semiconductor substrate. The second spacer layer is etched with a second spacer etchant to form second sidewall spacers.

    Abstract translation: 本文提供了制造集成电路的方法。 在一个实施例中，制造集成电路的方法包括形成覆盖半导体衬底的栅电极结构。 第一侧壁间隔件邻近栅电极结构的侧壁形成，并且第一侧壁间隔件包括氮化物。 在形成第一侧壁间隔物之后，将氧化物蚀刻剂施加到半导体衬底的表面。 包括氮化物的第二间隔物材料沉积在半导体衬底和第一侧壁间隔物上，以在将氧化物蚀刻剂施加到半导体衬底的表面之后形成第二间隔层。 用第二间隔物蚀刻剂蚀刻第二间隔层以形成第二侧壁间隔物。

    METHOD OF FORMING A SEMICONDUCTOR STRUCTURE INCLUDING SILICIDED AND NON-SILICIDED CIRCUIT ELEMENTS
    16.
    发明申请
    METHOD OF FORMING A SEMICONDUCTOR STRUCTURE INCLUDING SILICIDED AND NON-SILICIDED CIRCUIT ELEMENTS 有权
    形成含硅和非电解电路元件的半导体结构的方法

    公开(公告)号：US20150031179A1

    公开(公告)日：2015-01-29

    申请号：US14293627

    申请日：2014-06-02

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Dominic Thurmer ,  Sven Metzger ,  Joachim Patzer ,  Markus Lenski

    IPC: H01L21/283 ,  H01L29/66

    CPC classification number: H01L21/283 ,  H01L21/268 ,  H01L21/28518 ,  H01L21/823412 ,  H01L21/823418 ,  H01L27/0629 ,  H01L27/1104 ,  H01L29/665 ,  H01L29/7843 ,  H01L29/7847

    Abstract: A method includes providing a semiconductor structure including at least one first circuit element including a first semiconductor material and at least one second circuit element including a second semiconductor material. A dielectric layer having an intrinsic stress is formed that includes a first portion over the at least one first circuit element and a second portion over the at least one second circuit element. A first annealing process is performed, wherein an intrinsic stress is created at least in the first semiconductor material by stress memorization, and thereafter the first portion of the dielectric layer is removed. A layer of a metal is formed, and a second annealing process is performed, wherein the metal and the first semiconductor material react chemically to form a silicide. The second portion of the dielectric layer substantially prevents a chemical reaction between the second semiconductor material and the metal.

    Abstract translation: 一种方法包括提供包括至少一个包括第一半导体材料的第一电路元件和包括第二半导体材料的至少一个第二电路元件的半导体结构。 形成具有固有应力的电介质层，其包括至少一个第一电路元件上的第一部分和至少一个第二电路元件上的第二部分。 进行第一退火处理，其中通过应力记忆至少在第一半导体材料中产生固有应力，然后去除电介质层的第一部分。 形成金属层，进行第二退火处理，其中金属和第一半导体材料通过化学反应形成硅化物。 电介质层的第二部分基本上防止了第二半导体材料与金属之间的化学反应。

    METHODS OF FORMING A SEMICONDUCTOR DEVICE BY PERFORMING A WET ACID ETCHING PROCESS WHILE PREVENTING OR REDUCING LOSS OF ACTIVE AREA AND/OR ISOLATION REGIONS
    17.
    发明申请
    METHODS OF FORMING A SEMICONDUCTOR DEVICE BY PERFORMING A WET ACID ETCHING PROCESS WHILE PREVENTING OR REDUCING LOSS OF ACTIVE AREA AND/OR ISOLATION REGIONS 有权
    通过在预防或减少活动区域和/或分离区域的损失的同时进行湿酸蚀刻工艺来形成半导体器件的方法

    公开(公告)号：US20140227869A1

    公开(公告)日：2014-08-14

    申请号：US14172135

    申请日：2014-02-04

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Berthold Reimer ,  Markus Lenski ,  Bastian Haussdoerfer ,  Ardechir Pakfar

    IPC: H01L21/28 ,  H01L29/40

    CPC classification number: H01L29/401 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/78

    Abstract: One method disclosed includes forming a sidewall spacer proximate a gate structure, forming a sacrificial layer of material above a protective cap layer, the sidewall spacer and a substrate, forming a sacrificial protection layer above the sacrificial layer, reducing a thickness of the sacrificial protection layer such that its upper surface is positioned at a level that is below the upper surface of the protective cap layer, performing a first etching process to remove a portion of the sacrificial layer and thereby expose the protective cap layer for further processing, performing a wet acid etching process that includes diluted HF acid in the etch chemistry to remove the protective cap layer and performing at least one process operation to remove at least one of the reduced-thickness sacrificial protection layer or the sacrificial layer from above the surface of the substrate.

    Abstract translation: 所公开的一种方法包括在栅极结构附近形成侧壁间隔物，在保护盖层之上形成牺牲层材料，侧壁间隔物和衬底，在牺牲层上形成牺牲保护层，减小牺牲保护层的厚度 使得其上表面位于保护盖层的上表面下方的水平处，执行第一蚀刻工艺以去除牺牲层的一部分，从而露出保护盖层用于进一步处理，执行湿酸 蚀刻工艺，其在蚀刻化学中包括稀释的HF酸以去除保护盖层，并执行至少一个工艺操作以从衬底的表面上方去除至少一个减薄的牺牲保护层或牺牲层。

    SPACER FOR A GATE ELECTRODE HAVING TENSILE STRESS AND A METHOD OF FORMING THE SAME
    18.
    发明申请
    SPACER FOR A GATE ELECTRODE HAVING TENSILE STRESS AND A METHOD OF FORMING THE SAME 有权
    具有拉伸应力的门电极的间隔件及其形成方法

    公开(公告)号：US20140011302A1

    公开(公告)日：2014-01-09

    申请号：US14023966

    申请日：2013-09-11

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Hartmut Ruelke ,  Katja Huy ,  Markus Lenski

    IPC: H01L21/66

    CPC classification number: H01L22/10 ,  H01L21/3185 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843

    Abstract: By reducing a deposition rate and maintaining a low bias power in a plasma atmosphere, a spacer layer, for example a silicon nitride layer, may be deposited that exhibits tensile stress. The amount of tensile stress is controllable within a wide range, thereby providing the potential for forming sidewall spacer elements that modify the charge carrier mobility and thus the conductivity of the channel region of a field effect transistor.

    Abstract translation: 通过降低沉积速率并保持等离子体气氛中的低偏压功率，可以沉积显示拉伸应力的间隔层，例如氮化硅层。 拉伸应力的量在宽范围内是可控的，从而提供形成改变电场载流子迁移率并因此改变场效应晶体管的沟道区的导电性的侧壁间隔元件的潜力。

    WORK FUNCTION ADJUSTMENT IN HIGH-K METAL GATE ELECTRODE STRUCTURES BY SELECTIVELY REMOVING A BARRIER LAYER
    20.
    发明申请
    WORK FUNCTION ADJUSTMENT IN HIGH-K METAL GATE ELECTRODE STRUCTURES BY SELECTIVELY REMOVING A BARRIER LAYER 有权
    通过选择性去除障碍层，高K金属电极结构的工作功能调整

    公开(公告)号：US20130017679A1

    公开(公告)日：2013-01-17

    申请号：US13624235

    申请日：2012-09-21

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Markus Lenski ,  Klaus Hempel ,  Vivien Schroeder ,  Robert Binder ,  Joachim Metzger

    IPC: H01L21/28

    CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L21/82345 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

    Abstract: Generally, the present disclosure is directed work function adjustment in high-k metal gate electrode structures. In one illustrative embodiment, a method is disclosed that includes removing a placeholder material of a first gate electrode structure and a second gate electrode structure, and forming a first work function adjusting material layer in the first and second gate electrode structures, wherein the first work function adjusting material layer includes a tantalum nitride layer. The method further includes removing a portion of the first work function adjusting material layer from the second gate electrode structure by using the tantalum nitride layer as an etch stop layer, removing the tantalum nitride layer by performing a wet chemical etch process, and forming a second work function adjusting material layer in the second gate electrode structure and above a non-removed portion of the first work function adjusting material layer in the first gate electrode structure.

    Abstract translation: 通常，本公开涉及高k金属栅电极结构中的功函数调整。 在一个说明性实施例中，公开了一种方法，其包括移除第一栅极电极结构和第二栅电极结构的占位符材料，以及在第一和第二栅电极结构中形成第一功函数调节材料层，其中第一工件 功能调整材料层包括氮化钽层。 该方法还包括通过使用氮化钽层作为蚀刻停止层从第二栅极电极结构去除第一功函数调整材料层的一部分，通过执行湿化学蚀刻工艺去除氮化钽层，以及形成第二 第二栅电极结构中的功函数调整材料层，以及第一栅电极结构中的第一功函数调整材料层的未除去部分之上。

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