公开(公告)号：US10347541B1

公开(公告)日：2019-07-09

申请号：US15962808

申请日：2018-04-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  David Paul Brunco ,  Pei Liu ,  Shariq Siddiqui ,  Jinping Liu

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/08

Abstract: A method of forming contacts over active gates is provided. Embodiments include forming first and second gate structures over a portion of a fin; forming a first and second RSD in a portion of the fin between the first gate structures and between the first and the second gate structure, respectively; forming TS structures over the first and second RSD; forming a first cap layer over the first and second gate structures or over the TS structures; forming a metal oxide liner over the substrate, trenches formed; filling the trenches with a second cap layer; forming an ILD layer over the substrate; forming a CA through a first portion of the ILD and metal oxide layer down to the TS structures over the second RSD; and forming a CB through a second portion of the ILD and metal oxide layer down to the first gate structures.

公开(公告)号：US10062612B2

公开(公告)日：2018-08-28

申请号：US15288503

申请日：2016-10-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： David Paul Brunco ,  Daniel Jaeger

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/02

CPC classification number: H01L21/823431 ,  H01L21/02129 ,  H01L21/823481 ,  H01L21/823821 ,  H01L27/0886 ,  H01L29/66803

Abstract: Generally, the present disclosure is directed to a method for forming a FinFET device that may be used in designs that include both tight and relaxed fin pitches. The method for forming the fins includes: forming a first layer of doped silicate glass above a semiconductor wafer and within a plurality of recesses located adjacent the fins; forming a first layer of nitride above the first doped silicate glass layer; and forming a conformal oxide layer above the first nitride layer, substantially filling relatively narrow recesses between fins having a tight pitch and lining relatively wide recesses between fins having a relaxed pitch.

公开(公告)号：US20180175037A1

公开(公告)日：2018-06-21

申请号：US15894785

申请日：2018-02-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： David Paul Brunco

IPC: H01L27/092 ,  H01L29/06 ,  H01L21/762 ,  H01L29/10 ,  H01L29/167 ,  H01L21/306 ,  H01L21/02 ,  H01L21/8238 ,  H01L21/265

CPC classification number: H01L27/0924 ,  H01L21/02532 ,  H01L21/26513 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/0649 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/167

Abstract: At least one method, apparatus and system disclosed involves forming a finFET device having silicon and silicon germanium fins. The method includes: forming an n-doped and a p-doped region in a semiconductor wafer; forming a layer of silicon above both the those regions; removing a portion of the silicon layer above the p-doped region to create a first recess; forming a layer of silicon germanium in the first recess; etching away at least a portion of the silicon layer and the underlying p-doped region; etching away at least a portion of the silicon germanium layer and the underlying n-doped region; forming fins from the unetched silicon and silicon germanium layers; and forming a shallow trench isolation dielectric in the etched away portion of the silicon layer and the underlying p-doped region and in the etched away portion of the silicon germanium layer and the underlying n-doped region.

公开(公告)号：US09911740B2

公开(公告)日：2018-03-06

申请号：US15208495

申请日：2016-07-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： David Paul Brunco ,  Jeffrey Bowman Johnson

IPC: H01L27/088 ,  H01L27/092 ,  H01L21/265 ,  H01L21/762 ,  H01L21/225 ,  H01L21/02 ,  H01L29/167 ,  H01L21/8238 ,  H01L29/10

CPC classification number: H01L27/0924 ,  H01L21/02529 ,  H01L21/2251 ,  H01L21/26513 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/823892 ,  H01L29/1033 ,  H01L29/1083 ,  H01L29/167

Abstract: Generally, in one embodiment, the present disclosure is directed to a method for forming a transistor. The method includes: implanting a substrate to form at least one of an n and p doped region; depositing an epitaxial semiconductor layer over the substrate; forming trenches through the epitaxial layer and partially through at least one of an n and p doped region; forming dielectric isolation regions in the trenches; forming a fin in an upper portion of the epitaxial semiconductor layer by partially recessing the dielectric isolation regions; forming a gate dielectric adjacent at least two surfaces of the fin; and diffusing dopant from at least one of the n and p doped regions at least partially into the epitaxial semiconductor layer to form a diffusion doped transition region adjacent a bottom portion of the fin.

公开(公告)号：US09583557B2

公开(公告)日：2017-02-28

申请号：US14835278

申请日：2015-08-25

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Lili Cheng ,  Dina H. Triyoso ,  Jeasung Park ,  David Paul Brunco ,  Robert Fox ,  Sanford Chu

IPC: H01L21/00 ,  H01L49/02 ,  H01L23/522 ,  H01L21/02 ,  G06F17/50

CPC classification number: H01L28/60 ,  G06F17/5068 ,  H01L21/02181 ,  H01L21/02189 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits including a MIMCAP device and methods of forming the integrated circuits are provided. An exemplary method of forming an integrated circuit including a MIMCAP device includes pre-determining a thickness of at least one of a bottom high-K layer or a top high-K layer of the MIMCAP device, followed by fabricating the MIMCAP device. The pre-determined thickness is established based upon a pre-determined TDDB lifetime for the MIMCAP device and a minimum target capacitance density at an applied voltage bias to be employed for the MIMCAP device. The MIMCAP device includes a bottom electrode and a dielectric layer disposed over the bottom electrode. The dielectric layer includes a stack of individual layers including the bottom high-K layer, the top high-K layer, and a lower-K layer sandwiched therebetween. At least one of the bottom high-K layer or the top high-K layer has the pre-determined thickness.

Abstract translation: 提供了包括MIMCAP器件的集成电路和形成集成电路的方法。 形成包括MIMCAP器件的集成电路的示例性方法包括预先确定MIMCAP器件的底部高K层或顶部高K层中的至少之一的厚度，然后制造MIMCAP器件。 预先确定的厚度是基于MIMCAP器件的预定的TDDB寿命和MIMCAP器件所采用的施加电压偏置下的最小目标电容密度而建立的。 MIMCAP器件包括设置在底部电极上的底部电极和电介质层。 电介质层包括层叠的各层，包括底部高K层，顶部高K层和夹在其间的下部K层。 底部高K层或顶部高K层中的至少一层具有预定厚度。

公开(公告)号：US09490123B2

公开(公告)日：2016-11-08

申请号：US14523334

申请日：2014-10-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  David Paul Brunco

IPC: H01L21/20 ,  H01L21/70 ,  H01L21/762 ,  H01L21/36 ,  H01L21/302 ,  H01L21/461 ,  H01L21/02

CPC classification number: H01L21/02664 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/02694

Abstract: One illustrative method disclosed herein includes, among other things, sequentially forming a first material layer, a first capping layer, a second material layer and a second capping layer above a substrate, wherein the first and second material layers are made of semiconductor material having a lattice constant that is different than the substrate, the first material layer is strained as deposited, and a thickness of the first material layer exceeds its critical thickness required to be stable and strained, performing an anneal process after which the strain in the first material layer is substantially relaxed through the formation of crystallographic defects that are substantially confined to the semiconducting substrate, the first material layer, the first capping layer and the second material layer, and forming additional epitaxial semiconductor material on an upper surface of the resulting structure.

Abstract translation: 本文公开的一种说明性方法包括在衬底上顺序地形成第一材料层，第一覆盖层，第二材料层和第二覆盖层，其中第一和第二材料层由半导体材料制成，其具有 晶格常数不同于衬底，第一材料层被应变成沉积，并且第一材料层的厚度超过其要求稳定和应变的临界厚度，进行退火工艺，之后第一材料层中的应变 通过形成基本上限制于半导体衬底，第一材料层，第一覆盖层和第二材料层的晶体缺陷，以及在所得结构的上表面上形成附加的外延半导体材料而基本上松弛。

公开(公告)号：US20160118255A1

公开(公告)日：2016-04-28

申请号：US14523334

申请日：2014-10-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  David Paul Brunco

IPC: H01L21/02

CPC classification number: H01L21/02664 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/02694

Abstract: One illustrative method disclosed herein includes, among other things, sequentially forming a first material layer, a first capping layer, a second material layer and a second capping layer above a substrate, wherein the first and second material layers are made of semiconductor material having a lattice constant that is different than the substrate, the first material layer is strained as deposited, and a thickness of the first material layer exceeds its critical thickness required to be stable and strained, performing an anneal process after which the strain in the first material layer is substantially relaxed through the formation of crystallographic defects that are substantially confined to the semiconducting substrate, the first material layer, the first capping layer and the second material layer, and forming additional epitaxial semiconductor material on an upper surface of the resulting structure.

Abstract translation: 本文公开的一种说明性方法包括在衬底上顺序地形成第一材料层，第一覆盖层，第二材料层和第二覆盖层，其中第一和第二材料层由半导体材料制成，其具有 晶格常数不同于衬底，第一材料层被应变成沉积，并且第一材料层的厚度超过其要求稳定和应变的临界厚度，进行退火工艺，之后第一材料层中的应变 通过形成基本上限制于半导体衬底，第一材料层，第一覆盖层和第二材料层的晶体缺陷，以及在所得结构的上表面上形成附加的外延半导体材料而基本上松弛。

公开(公告)号：US20150146341A1

公开(公告)日：2015-05-28

申请号：US14092431

申请日：2013-11-27

Applicant: GLOBALFOUNDRIES, Inc. ,  Intermolecular Inc.

Inventor： Nobumichi Fuchigami ,  David Paul Brunco ,  Karthik Ramani ,  Dina Triyoso

IPC: H01G4/10 ,  C23C16/455 ,  H01G4/30

CPC classification number: H01G4/10 ,  C23C16/403 ,  C23C16/405 ,  C23C16/45525 ,  H01G4/085 ,  H01G4/1281 ,  H01G4/306 ,  H01G4/33 ,  H01L28/40

Abstract: A thin sub-layer ( 12) host material. The sub-layer may be formed by atomic layer deposition (ALD). The layer and sub-layer are annealed to form a composite dielectric layer. The host material crystallizes, but the crystalline lattice and grain boundaries are disrupted near the impurity sub-layer, impeding the migration of electrons. The impurity may be a material with a lower dielectric constant than the high-k material, added in such a small relative amount that the composite dielectric is still high-k. Metal-insulator-metal capacitors may be fabricated by forming the composite dielectric layer between two electrodes.

Abstract translation: 在高k（k> 12）主体材料的较厚层（〜30-100）的下面，上方或内部形成杂质的薄亚层（<15Å）。 子层可以通过原子层沉积（ALD）形成。 层和子层进行退火以形成复合介电层。 主体材料结晶，但晶格和晶界在杂质子层附近被破坏，阻碍了电子迁移。 杂质可以是具有比高k材料低的介电常数的材料，以如此小的相对量添加复合电介质仍然高k。 可以通过在两个电极之间形成复合介电层来制造金属 - 绝缘体 - 金属电容器。

公开(公告)号：US09029217B1

公开(公告)日：2015-05-12

申请号：US14592412

申请日：2015-01-08

Applicant: IMEC ,  GlobalFoundries Inc.

Inventor： Benjamin Vincent ,  Geert Hellings ,  David Paul Brunco

IPC: H01L21/336 ,  H01L29/94 ,  H01L29/66 ,  H01L29/161 ,  H01L21/02 ,  H01L29/10

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/0257 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/785 ,  H01L29/7856

Abstract: The disclosure is related to a band engineered semiconductor device comprising a substrate and a protruding structure that is formed in a recess in the substrate. The protruding structure extends above the recess and has a buried portion and an extended portion. At least the extended portion comprises a semiconductor material having an inverted ‘V’ band gap profile with a band gap value increasing gradually from a first value at lateral edges of the structure to a second value, higher than the first value, in a center of the structure. The disclosure is also related to the method of manufacturing of such a band engineered semiconductor device.

Abstract translation: 本公开涉及一种带状工程半导体器件，其包括衬底和形成在衬底中的凹部中的突出结构。 突出结构在凹部上方延伸并具有埋设部分和延伸部分。 至少延伸部分包括具有倒置的“V”带隙轮廓的半导体材料，带隙值从结构的横向边缘处的第一值逐渐增加到高于第一值的第二值，高于第一值 结构。 本公开还涉及制造这种带状工程半导体器件的方法。

公开(公告)号：US20150126010A1

公开(公告)日：2015-05-07

申请号：US14592412

申请日：2015-01-08

Applicant: IMEC ,  GLOBALFOUNDRIES INC.

Inventor： Benjamin Vincent ,  Geert Hellings ,  David Paul Brunco

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/10 ,  H01L29/161

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/0257 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/785 ,  H01L29/7856

Abstract: The disclosure is related to a band engineered semiconductor device comprising a substrate and a protruding structure that is formed in a recess in the substrate. The protruding structure extends above the recess and has a buried portion and an extended portion. At least the extended portion comprises a semiconductor material having an inverted ‘V’ band gap profile with a band gap value increasing gradually from a first value at lateral edges of the structure to a second value, higher than the first value, in a center of the structure. The disclosure is also related to the method of manufacturing of such a band engineered semiconductor device.

Abstract translation: 本公开涉及一种带状工程半导体器件，其包括衬底和形成在衬底中的凹部中的突出结构。 突出结构在凹部上方延伸并具有埋设部分和延伸部分。 至少延伸部分包括具有倒置的“V”带隙轮廓的半导体材料，带隙值从结构的横向边缘处的第一值逐渐增加到高于第一值的第二值，高于第一值 结构。 本公开还涉及制造这种带状工程半导体器件的方法。