公开(公告)号：US09209274B2

公开(公告)日：2015-12-08

申请号：US13946103

申请日：2013-07-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Gerd Zschaetzsch ,  Stefan Flachowsky ,  Dominic Thurmer

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/225 ,  H01L21/8234

CPC classification number: H01L27/1211 ,  H01L21/2254 ,  H01L21/823431 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/66803 ,  H01L29/7834 ,  H01L29/785

Abstract: The present disclosure provides in various aspects methods of forming a semiconductor device, methods for forming a semiconductor device structure, a semiconductor device and a semiconductor device structure. In some illustrative embodiments herein, a gate structure is formed over a non-planar surface portion of a semiconductor material provided on a surface of a substrate. A doped spacer-forming material is formed over the gate structure and the semiconductor material and dopants incorporated in the doped spacer-forming material are diffused into the semiconductor material close to a surface of the semiconductor material so as to form source/drain extension regions. The fabricated semiconductor devices may be multi-gate devices and, for example, comprise finFETs and/or wireFETs.

Abstract translation: 本公开在各方面提供了形成半导体器件的方法，形成半导体器件结构的方法，半导体器件和半导体器件结构。 在本文的一些说明性实施例中，栅极结构形成在设置在基板的表面上的半导体材料的非平面表面部分上。 掺杂的间隔物形成材料形成在栅极结构上，并且半导体材料和并入掺杂的间隔物形成材料中的掺杂剂被扩散到靠近半导体材料的表面的半导体材料中，以形成源极/漏极延伸区域。 制造的半导体器件可以是多栅极器件，并且例如包括finFET和/或wireFET。

公开(公告)号：US09177874B2

公开(公告)日：2015-11-03

申请号：US14012563

申请日：2013-08-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Joachim Patzer ,  Ardechir Pakfar ,  Dominic Thurmer ,  Chih-Chun Wang ,  Remi Riviere ,  Robert Melzer ,  Bastian Haussdoerfer ,  Martin Weisheit

IPC: H01L21/00 ,  H01L21/66 ,  H01L21/8238 ,  H01L27/06 ,  H01L21/311 ,  H01L21/3105

CPC classification number: H01L22/12 ,  H01L21/31058 ,  H01L21/31144 ,  H01L21/823828 ,  H01L21/823878 ,  H01L22/20 ,  H01L27/0629

Abstract: A method for the manufacture of a semiconductor device is provided, including the steps of providing a semiconductor substrate including a first area separated from a second area by a first isolation region, wherein the second area includes an intermediate transistor comprising a gate electrode, forming an oxide layer over the first and second areas, forming an optical planarization layer (OPL) over the oxide layer, forming a mask layer over the OPL in the first area without covering the OPL in the second area, and etching the OPL with the mask layer being present to expose the oxide layer over the gate electrode of the transistor.

Abstract translation: 提供了一种用于制造半导体器件的方法，包括以下步骤：提供包括由第一隔离区域与第二区域分离的第一区域的半导体衬底，其中第二区域包括包括栅电极的中间晶体管，形成 在所述第一区域和所述第二区域上形成氧化物层，在所述氧化物层上形成光学平坦化层（OPL），在所述第一区域中的所述OPL上形成掩模层，而不覆盖所述第二区域中的所述OPL，并且用所述掩模层 存在以将氧化物层暴露在晶体管的栅电极之上。

公开(公告)号：US20150064812A1

公开(公告)日：2015-03-05

申请号：US14012563

申请日：2013-08-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Joachim Patzer ,  Ardechir Pakfar ,  Dominic Thurmer ,  Chih-Chun Wang ,  Remi Riviere ,  Robert Melzer ,  Bastian Haussdoerfer ,  Martin Weisheit

IPC: H01L21/311 ,  H01L21/66

CPC classification number: H01L22/12 ,  H01L21/31058 ,  H01L21/31144 ,  H01L21/823828 ,  H01L21/823878 ,  H01L22/20 ,  H01L27/0629

Abstract: A method for the manufacture of a semiconductor device is provided, including the steps of providing a semiconductor substrate including a first area separated from a second area by a first isolation region, wherein the second area includes an intermediate transistor comprising a gate electrode, forming an oxide layer over the first and second areas, forming an organic planarization layer (OPL) over the oxide layer, forming a mask layer over the OPL in the first area without covering the OPL in the second area, and etching the OPL with the mask layer being present to expose the oxide layer over the gate electrode of the transistor.

Abstract translation: 提供了一种用于制造半导体器件的方法，包括以下步骤：提供包括由第一隔离区域与第二区域分离的第一区域的半导体衬底，其中第二区域包括包括栅电极的中间晶体管，形成 在所述第一区域和所述第二区域上形成氧化物层，在所述氧化物层上形成有机平坦化层（OPL），在所述第一区域中的OPL上形成掩模层，而不覆盖所述第二区域中的所述OPL，并且用所述掩模层 存在以将氧化物层暴露在晶体管的栅电极之上。

公开(公告)号：US20150021712A1

公开(公告)日：2015-01-22

申请号：US13946103

申请日：2013-07-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Gerd Zschaetzsch ,  Stefan Flachowsky ,  Dominic Thurmer

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L27/1211 ,  H01L21/2254 ,  H01L21/823431 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/66803 ,  H01L29/7834 ,  H01L29/785

Abstract: The present disclosure provides in various aspects methods of forming a semiconductor device, methods for forming a semiconductor device structure, a semiconductor device and a semiconductor device structure. In some illustrative embodiments herein, a gate structure is formed over a non-planar surface portion of a semiconductor material provided on a surface of a substrate. A doped spacer-forming material is formed over the gate structure and the semiconductor material and dopants incorporated in the doped spacer-forming material are diffused into the semiconductor material close to a surface of the semiconductor material so as to form source/drain extension regions. The fabricated semiconductor devices may be multi-gate devices and, for example, comprise finFETs and/or wireFETs.

Abstract translation: 本公开在各方面提供了形成半导体器件的方法，形成半导体器件结构的方法，半导体器件和半导体器件结构。 在本文的一些说明性实施例中，栅极结构形成在设置在基板的表面上的半导体材料的非平面表面部分上。 掺杂的间隔物形成材料形成在栅极结构上，并且半导体材料和并入掺杂的间隔物形成材料中的掺杂剂被扩散到靠近半导体材料的表面的半导体材料中，以形成源极/漏极延伸区域。 制造的半导体器件可以是多栅极器件，并且例如包括finFET和/或wireFET。

公开(公告)号：US08906794B1

公开(公告)日：2014-12-09

申请号：US13956844

申请日：2013-08-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Joachim Patzer ,  Ardechir Pakfar ,  Clemens Fitz ,  Dominic Thurmer

IPC: H01L21/00 ,  H01L27/088 ,  H01L21/28

CPC classification number: H01L21/823443 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/32053 ,  H01L21/321 ,  H01L21/324 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/4925 ,  H01L29/4933

Abstract: A method for performing silicidation of gate electrodes includes providing a semiconductor device having first and second transistors with first and second gate electrodes formed on a semiconductor substrate, forming an oxide layer on the first and second gate electrodes and the semiconductor substrate, forming a cover layer on the oxide layer, and back etching the cover layer to expose portions of the oxide layer above the first and second gate electrodes while maintaining a portion of the cover layer between the first and second gate electrodes. Furthermore, the exposed portions of the oxide layer are removed from the first and second gate electrodes to expose upper portions of the first and second gate electrodes, while maintaining a portion of the oxide layer between the first and second gate electrodes, and a silicidation of the exposed upper portions of the first and second gate electrodes is performed.

Abstract translation: 一种用于执行栅电极的硅化的方法包括提供具有第一和第二晶体管的半导体器件，其中第一和第二栅电极形成在半导体衬底上，在第一和第二栅电极和半导体衬底上形成氧化物层，形成覆盖层 在所述氧化物层上，并且背面蚀刻所述覆盖层以暴露所述第一和第二栅电极之上的所述氧化物层的部分，同时保持所述覆盖层的所述第一和第二栅电极之间的一部分。 此外，从第一和第二栅电极去除氧化层的暴露部分，以暴露第一和第二栅电极的上部，同时保持第一和第二栅电极之间的氧化物层的一部分，以及硅化 执行第一和第二栅电极的暴露的上部。