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    Methods, apparatus and system determining dual port DC contention margin
    12.
    发明授权
    Methods, apparatus and system determining dual port DC contention margin 有权
    方法，设备和系统确定双端口DC争用余量

    公开(公告)号：US09530488B1

    公开(公告)日：2016-12-27

    申请号：US15048583

    申请日：2016-02-19

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Sriram Balasubramanian ,  Vivek Joshi ,  Randy W. Mann ,  Ratheesh Ramachandran Thankalekshmi

    IPC: G11C29/50 ,  G11C11/419 ,  G11C29/44

    CPC classification number: G11C11/419 ,  G11C8/16 ,  G11C29/028 ,  G11C29/44 ,  G11C29/50

    Abstract: At least one method, apparatus and system disclosed involves testing a dual port memory cell in a memory device. A semiconductor wafer is processed for providing a dual port memory device. An inline DC contention margin test is performed for testing a contention margin related to a write operation into a cell of the memory device. A determination is made as to whether the contention margin is within a predetermined range. A responsive action is performed in response to determining that the contention margin is outside the predetermined range.

    Abstract translation: 所公开的至少一种方法，装置和系统涉及测试存储器装置中的双端口存储单元。 处理半导体晶片以提供双端口存储器件。 执行在线DC争用余量测试，用于测试与写入操作相关的争用余量到存储器件的单元中。 确定争用余额是否在预定范围内。 响应于确定争用余量在预定范围之外来执行响应动作。

    Wafer test structures and methods of providing wafer test structures
    13.
    发明授权
    Wafer test structures and methods of providing wafer test structures 有权
    晶圆测试结构和提供晶圆测试结构的方法

    公开(公告)号：US09372226B2

    公开(公告)日：2016-06-21

    申请号：US14337290

    申请日：2014-07-22

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Suresh Uppal ,  Randy W. Mann ,  William McMahon

    IPC: G06F17/00 ,  G01R31/28 ,  H01L23/525 ,  H01L21/66

    CPC classification number: G01R31/2884 ,  G01R31/2644 ,  H01L22/14 ,  H01L22/34 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Wafer test structures and methods of providing wafer test structures are described. The methods include: fabricating multiple test devices and multiple fuse devices on the wafer, each test device having a respective fuse device associated therewith, which open circuits upon failure of the test device; and fabricating a selection circuit operative to selectively connect one test device to a sense contact pad, and the other test devices to a stress contact pad. The selection circuit facilitates sensing one or more electrical signals of the one test device by electrical contact with the sense contact pad, while stress testing the other test devices by electrical contact with the stress contact pad. In one embodiment, each test device has respective first and second switch devices, operative to selectively electrically connect the test device to the sense or stress contact pads. In another embodiment, the method includes wafer testing using the test structure.

    Abstract translation: 描述了晶片测试结构和提供晶片测试结构的方法。 这些方法包括：在晶片上制造多个测试装置和多个保险丝装置，每个测试装置具有与其相关联的相应的熔丝装置，其在测试装置故障时断开电路; 以及制造选择电路，其操作以选择性地将一个测试装置连接到感测触点焊盘，并且将其它测试装置连接到应力接触焊盘。 选择电路通过与感测接触焊盘的电接触便于感测一个测试装置的一个或多个电信号，同时通过与应力接触焊盘电接触来测试其它测试装置。 在一个实施例中，每个测试装置具有相应的第一和第二开关装置，其可操作以选择性地将测试装置电连接到感测或应力接触垫。 在另一个实施例中，该方法包括使用测试结构的晶片测试。

    METHOD OF REDUCING FIN WIDTH IN FINFET SRAM ARRAY TO MITIGATE LOW VOLTAGE STRAP BIT FAILS
    14.
    发明申请
    METHOD OF REDUCING FIN WIDTH IN FINFET SRAM ARRAY TO MITIGATE LOW VOLTAGE STRAP BIT FAILS 审中-公开

    公开(公告)号：US20180261605A1

    公开(公告)日：2018-09-13

    申请号：US15603827

    申请日：2017-05-24

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Xiaoqiang Zhang ,  Hui Zang ,  Ratheesh R. Thankalekshmi ,  Randy W. Mann

    IPC: H01L27/11 ,  H01L29/66

    CPC classification number: H01L27/1104 ,  H01L29/66545 ,  H01L29/66818

    Abstract: A method of reducing fin width in an integrated circuit (IC) including oxidizing an exposed portion of at least one fin in an array of fins resulting in a reduction in the width of the exposed portion of the at least one fin. A first hard mask may be located over the array of fins except the exposed portion of the at least one fin during oxidation. A second hard mask may be optionally located over the array of fins, under the first hard mask, and covering a portion of the exposed portion of the at least one fin during the oxidizing of the exposed portion of the at least one fin. The oxidizing the exposed portion of the at least one fin may occur before forming a shallow trench isolation (STI) between pairs of fins in the array of fins, after forming the STI between the pairs of fins in the array of fins, and/or after removing a dummy gate during a replacement metal gate process.

    INTEGRATED CIRCUIT WITH A FIN-BASED FUSE, AND RELATED FABRICATION METHOD
    17.
    发明申请
    INTEGRATED CIRCUIT WITH A FIN-BASED FUSE, AND RELATED FABRICATION METHOD 有权
    具有熔点熔丝的集成电路及相关制造方法

    公开(公告)号：US20140021579A1

    公开(公告)日：2014-01-23

    申请号：US14032484

    申请日：2013-09-20

    Applicant: GLOBALFOUNDRIES, Inc.

    Inventor： Randy W. Mann ,  Kingsuk Maitra ,  Anurag Mittal

    IPC: H01L23/62

    CPC classification number: H01L23/62 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Methods of fabricating an integrated circuit with a fin-based fuse, and the resulting integrated circuit with a fin-based fuse are provided. In the method, a fin is created from a layer of semiconductor material and has a first end and a second end. The method provides for forming a conductive path on the fin from its first end to its second end. The conductive path is electrically connected to a programming device that is capable of selectively directing a programming current through the conductive path to cause a structural change in the conductive path to increase resistance across the conductive path.

    Abstract translation: 提供了制造具有鳍式保险丝的集成电路的方法，以及所得到的具有鳍式保险丝的集成电路。 在该方法中，由半导体材料层产生翅片并具有第一端和第二端。 该方法提供了在翅片上从其第一端到其第二端形成导电路径。 导电路径电连接到编程设备，该编程设备能够选择性地将编程电流引导通过导电路径，从而导致导电路径中的结构变化，以增加穿过导电路径的电阻。

    Structures and SRAM bit cells integrating complementary field-effect transistors
    18.
    发明授权
    Structures and SRAM bit cells integrating complementary field-effect transistors 有权

    公开(公告)号：US10818674B2

    公开(公告)日：2020-10-27

    申请号：US16295485

    申请日：2019-03-07

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Randy W. Mann ,  Bipul C. Paul ,  Julien Frougier ,  Ruilong Xie

    IPC: H01L27/11 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L27/092

    Abstract: Structures and static random access memory bit cells including complementary field effect transistors and methods of forming such structures and bit cells. A first complementary field-effect transistor has a first storage nanosheet transistor, a second storage nanosheet transistor stacked over the first storage nanosheet transistor, and a first gate electrode shared by the first storage nanosheet transistor and the second storage nanosheet transistor. A second complementary field-effect transistor has a third storage nanosheet transistor, a fourth storage nanosheet transistor stacked over the third storage nanosheet transistor, and a second gate electrode shared by the third storage nanosheet transistor and the fourth storage nanosheet transistor. The first gate electrode and the second gate electrode are arranged in a spaced arrangement along a longitudinal axis. All gate electrodes of the SRAM bitcell may be arranged in a 1CPP layout.

    Dual port vertical transistor memory cell
    19.
    发明授权
    Dual port vertical transistor memory cell 有权

    公开(公告)号：US10439064B1

    公开(公告)日：2019-10-08

    申请号：US15990956

    申请日：2018-05-29

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Randy W. Mann ,  Bipul C. Paul

    IPC: H01L23/528 ,  H01L29/78 ,  H01L29/66 ,  H01L27/11 ,  H01L27/092

    Abstract: A first S/D region includes a first P-type region, a first N-type region, and a first conductive layer thereon to define a first cell node. A second S/D region includes a second P-type region, a second N-type region, and a second conductive layer thereon to define a second cell node. A PDL transistor and PGLA, PGLB transistors have bottom SD regions in the first N-type region. A PUL transistor has a bottom SD region positioned in the first P-type region. A PDR transistor and PGRA, PGRB have bottom SD regions in the second N-type region. A PUR transistor has a bottom SD region in the second P-type region. A first gate is positioned around channel regions of the PUL and PDL transistors and conductively coupled to the second node. A second gate is positioned around channel regions of the PUR and PDR transistors and conductively coupled to the first node.

    NOVEL SIX-TRANSISTOR (6T) SRAM CELL STRUCTURE
    20.
    发明申请
    NOVEL SIX-TRANSISTOR (6T) SRAM CELL STRUCTURE 审中-公开

    公开(公告)号：US20190139967A1

    公开(公告)日：2019-05-09

    申请号：US15804556

    申请日：2017-11-06

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Randy W. Mann ,  Bipul C. Paul

    IPC: H01L27/11 ,  G11C11/412 ,  H01L27/092

    CPC classification number: H01L27/1104 ,  G11C11/412 ,  H01L27/092 ,  H01L2027/11816

    Abstract: One illustrative 6T SRAM cell structure disclosed herein includes a first active region with a first N-type pass gate transistor, a first N-type pull-down transistor and a first P-type pull-up transistor, each of which are formed in and above the first active region, wherein the first N-type pull-down transistor is positioned laterally between the first N-type pass gate transistor and the first P-type pull-up transistor, and a second active region with a second N-type pass gate transistor, a second N-type pull-down transistor and a second P-type pull-up transistor, each of which are formed in and above the second active region, wherein the second N-type pull-down transistor is positioned laterally between the second N-type pass gate transistor and the second P-type pull-up transistor.

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