公开(公告)号：US20200176589A1

公开(公告)日：2020-06-04

申请号：US16207915

申请日：2018-12-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Siva P. Adusumilli ,  John J. Ellis-Monaghan ,  Anthony K. Stamper ,  Ian McCallum-Cook ,  Mark Goldstein

IPC: H01L29/66 ,  H01L29/786 ,  H01L21/265 ,  H01L21/762 ,  C23C16/40 ,  C23C16/48

Abstract: Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. A semiconductor layer is implanted over a first depth range of an inert gas species to modify the crystal structure of a semiconductor material of the semiconductor layer and form a first modified region. The semiconductor layer is annealed with a first annealing process to convert the semiconductor material within the first modified region to a non-single-crystal layer. The semiconductor layer is also implanted with ions of an element over a second depth range to modify the crystal structure of the semiconductor material of the semiconductor layer and form a second modified region containing a concentration of the element. The semiconductor layer is annealed with a second annealing process to convert the semiconductor material within the second modified region to an insulator layer containing the element.

公开(公告)号：US10466514B1

公开(公告)日：2019-11-05

申请号：US16181879

申请日：2018-11-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven M. Shank ,  Siva P. Adusumilli

IPC: G02F1/035 ,  G02F1/225 ,  G02B6/122 ,  G02B6/136 ,  F21V8/00 ,  G02F1/015 ,  G02F1/21 ,  G02B6/12

Abstract: Structures for an electro-optic modulator and methods of fabricating such structures. A first plurality of cavities are formed in a bulk semiconductor substrate. A passive waveguide arm includes a first core arranged over the first plurality of cavities. The passive waveguide arm has an input port and an output port that is spaced lengthwise from the input port. An epitaxial semiconductor layer is arranged over the bulk semiconductor substrate, and includes a second plurality of cavities. An active waveguide arm includes a second core that is arranged over the second plurality of cavities. The second core of the active waveguide arm is coupled with the input port of the first core of the passive waveguide arm, and the second core of the active waveguide arm is also coupled with the output port of the first core of the passive waveguide arm.

公开(公告)号：US20190295881A1

公开(公告)日：2019-09-26

申请号：US16218868

申请日：2018-12-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven M. Shank ,  Anthony K. Stamper ,  Ian McCallum-Cook ,  Siva P. Adusumilli

IPC: H01L21/763 ,  H01L29/06 ,  H01L21/84 ,  H01L27/12 ,  H01L27/06 ,  H01L21/762 ,  H01L21/265 ,  H01L21/324

Abstract: Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. Trench isolation regions surround an active device region composed of a single-crystal semiconductor material. A first non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. A second non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. The first non-single-crystal layer is arranged between the second non-single-crystal layer and the active device region.

公开(公告)号：US20190265406A1

公开(公告)日：2019-08-29

申请号：US15905165

申请日：2018-02-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven M. Shank ,  Siva P. Adusumilli

IPC: G02B6/122 ,  G02B6/13 ,  G02B6/132 ,  G02B6/136

Abstract: Waveguide structures and methods of fabricating waveguide structures. A first airgap is formed in a bulk semiconductor substrate, and a semiconductor layer is epitaxially grown over the bulk semiconductor substrate and the first airgap. First and second trench isolation regions extend through the semiconductor layer and into the bulk semiconductor substrate, and are spaced to define a waveguide core region including a section of the bulk semiconductor substrate and a section of the semiconductor layer that are arranged between the first and second trench isolation regions. A dielectric layer is formed over the waveguide core region, and a second airgap is formed in the dielectric layer. The first airgap is arranged in the bulk semiconductor substrate between the first trench isolation region and the second trench isolation region and under the waveguide core region. The second airgap in the dielectric layer is arranged over the waveguide core region.

公开(公告)号：US10263013B2

公开(公告)日：2019-04-16

申请号：US15441711

申请日：2017-02-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Steven M. Shank ,  Siva P. Adusumilli

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/84 ,  H01L49/02 ,  H01L21/265 ,  H01L29/08 ,  H01L29/45 ,  H01L27/06 ,  H01L29/06

Abstract: Disclosed is an integrated circuit (IC) formation method, wherein trenches are formed within a semiconductor layer to define semiconductor mesa(s). Instead of immediately filling the trenches with an isolation material and performing a planarizing process to complete the STI regions prior to device formation, the method initially only form sidewall spacers within the trenches on the exposed sidewalls of the semiconductor mesa(s). After the sidewall spacers are formed, device(s) (e.g., field effect transistor(s), silicon resistor(s), etc.) are formed using the semiconductor mesa(s) and, optionally, additional device(s) (e.g., polysilicon resistor(s)) can be formed within the trenches between adjacent semiconductor mesas. Subsequently, middle of the line (MOL) dielectrics (e.g., a conformal etch stop layer and a blanket interlayer dielectric (ILD) layer) are deposited over the device(s), thereby filling any remaining space within the trenches and completing the STI regions. Also disclosed is an IC structure formed using the method.

公开(公告)号：US20190074364A1

公开(公告)日：2019-03-07

申请号：US15693537

申请日：2017-09-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Laura J. Schutz ,  Anthony K. Stamper ,  Siva P. Adusumilli ,  Joshua F. Dillon

IPC: H01L29/49 ,  H01L29/417 ,  H01L29/423 ,  H01L21/8234 ,  H01L21/3205 ,  H01L29/66

CPC classification number: H01L29/4991 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/32053 ,  H01L21/76224 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/41758 ,  H01L29/4232 ,  H01L29/4238 ,  H01L29/4933 ,  H01L29/4975 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66575

Abstract: A method may include forming a transistor on a substrate, the transistor including a gate, and forming a sacrificial spacer extending along an entirety of a thickness of the gate. A via layer is then formed over/about the gate. The sacrificial spacer is at least partially removed, leaving an air vent opening. An airgap spacer is formed in the dielectric layer by depositing another dielectric layer to close off the air vent opening. The airgap spacer is coincident with at least one sidewall of the gate and extends along an entirety of a thickness of the gate. Gate airgaps may also be provided over the gate. Other embodiments extend the gate and airgap spacer the full thickness of the dielectric layer thereabout. Other embodiments extend the airgap spacer over the gate.

公开(公告)号：US10192779B1

公开(公告)日：2019-01-29

申请号：US15935606

申请日：2018-03-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven M. Shank ,  Anthony K. Stamper ,  Ian McCallum-Cook ,  Siva P. Adusumilli

IPC: H01L21/763 ,  H01L29/06 ,  H01L27/12 ,  H01L27/06 ,  H01L21/762 ,  H01L21/324 ,  H01L21/84 ,  H01L21/265 ,  H01L21/02

Abstract: Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. Trench isolation regions surround an active device region composed of a single-crystal semiconductor material. A non-single-crystal layer has a first section arranged beneath the trench isolation regions and a second section arranged beneath the active device region. The first section of the non-single-crystal layer has a first width in a vertical direction. The second section of the non-single-crystal layer has a second width in the vertical direction that is less than the first width of the first section of the non-single-crystal layer.

公开(公告)号：US11527432B2

公开(公告)日：2022-12-13

申请号：US17086925

申请日：2020-11-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven M. Shank ,  Anthony K. Stamper ,  Ian McCallum-Cook ,  Siva P. Adusumilli

IPC: H01L21/763 ,  H01L29/06 ,  H01L27/12 ,  H01L21/762 ,  H01L21/324 ,  H01L21/84 ,  H01L21/265 ,  H01L21/74 ,  H01L29/32 ,  H01L21/02 ,  H01L27/06 ,  H01L29/10

Abstract: Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. Trench isolation regions surround an active device region composed of a single-crystal semiconductor material. A first non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. A second non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. The first non-single-crystal layer is arranged between the second non-single-crystal layer and the active device region.

公开(公告)号：US10923577B2

公开(公告)日：2021-02-16

申请号：US16241441

申请日：2019-01-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Johnatan A. Kantarovsky ,  Siva P. Adusumilli ,  Vibhor Jain

IPC: H01L29/00 ,  H01L29/51 ,  H01L21/762 ,  H01L49/02 ,  H01L29/161 ,  H01L21/3065 ,  H01L21/02 ,  H01L29/06 ,  H01L21/3105 ,  H01L21/764

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to cavity structures under shallow trench isolation regions and methods of manufacture. The structure includes: one or more cavity structures provided in a substrate material and sealed with an epitaxial material; and a shallow trench isolation region directly above the one or more cavity structures in the substrate material.

公开(公告)号：US20210043624A1

公开(公告)日：2021-02-11

申请号：US16534361

申请日：2019-08-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Siva P. Adusumilli ,  Julien Frougier ,  Ruilong Xie ,  Anthony K. Stamper

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/324 ,  H01L29/04

Abstract: Structures with altered crystallinity and methods associated with forming such structures. A semiconductor layer has a first region containing polycrystalline semiconductor material, defects, and atoms of an inert gas species. Multiple fins are arranged over the first region of the semiconductor layer. The structure may be formed by implanting the semiconductor layer with inert gas ions to modify a crystal structure of the semiconductor layer in the first region and a second region between the first region and a top surface of the semiconductor layer. An annealing process is used to convert the first region of the semiconductor layer to a polycrystalline state and the second region of the semiconductor layer to a monocrystalline state. The fins are patterned from the second region of the semiconductor layer and another semiconductor layer epitaxially grown over the second region of the semiconductor layer.