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    Anchored stress-generating active semiconductor regions for semiconductor-on-insulator finfet
    12.
    发明授权
    Anchored stress-generating active semiconductor regions for semiconductor-on-insulator finfet 有权
    用于半导体绝缘体finfet的锚定应力产生有源半导体区域

    公开(公告)号：US09349863B2

    公开(公告)日：2016-05-24

    申请号：US13961522

    申请日：2013-08-07

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Veeraraghavan S. Basker ,  Krishna Iyengar ,  Tenko Yamashita ,  Chun-Chen Yeh

    IPC: H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L29/165

    CPC classification number: H01L29/66795 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/7848 ,  H01L29/785

    Abstract: After formation of a gate structure and a gate spacer, portions of an insulator layer underlying a semiconductor fin are etched to physically expose semiconductor surfaces of an underlying semiconductor material layer from underneath a source region and a drain region. Each of the extended source region and the extended drain region includes an anchored single crystalline semiconductor material portion that is in epitaxial alignment to the single crystalline semiconductor structure of the underlying semiconductor material layer and laterally applying a stress to the semiconductor fin. Because each anchored single crystalline semiconductor material portion is in epitaxial alignment with the underlying semiconductor material layer, the channel of the fin field effect transistor is effectively stressed along the lengthwise direction of the semiconductor fin.

    Abstract translation: 在形成栅极结构和栅极间隔物之后，蚀刻半导体鳍片下面的绝缘体层的部分，以从源极区域和漏极区域下面物理地暴露下面的半导体材料层的半导体表面。 扩展源极区域和延伸漏极区域中的每一个包括锚定的单晶半导体材料部分，其与下面的半导体材料层的单晶半导体结构外延对准，并向半导体鳍片横向施加应力。 因为每个锚定的单晶半导体材料部分与下面的半导体材料层进行外延对准，所以鳍状场效应晶体管的沟道沿着半导体鳍片的长度方向被有效地应力。

    Fin field effect transistor including asymmetric raised active regions
    18.
    发明授权
    Fin field effect transistor including asymmetric raised active regions 有权
    Fin场效应晶体管包括不对称凸起的有源区

    公开(公告)号：US09553032B2

    公开(公告)日：2017-01-24

    申请号：US15092233

    申请日：2016-04-06

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Ali Khakifirooz

    IPC: H01L21/336 ,  H01L21/84 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L27/12 ,  H01L21/265 ,  H01L21/266 ,  H01L29/32

    CPC classification number: H01L21/845 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L27/1211 ,  H01L29/32 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  H01L29/7856

    Abstract: Merged and unmerged raised active regions on semiconductor fins can be simultaneously formed on a same substrate by control of growth rates of a deposited semiconductor material on surfaces of the semiconductor fins. In one embodiment, a growth-rate-retarding dopant can be implanted by angled ion implantation onto sidewall surfaces of first semiconductor fins on which retardation of growth rates is desired, while second semiconductor fins are masked by a masking layer. In another embodiment, a growth-rate-enhancing dopant can be implanted by ion implantation onto sidewall surfaces of second semiconductor fins, while first semiconductor fins are masked by a masking layer. The differential growth rates of the deposited semiconductor material can cause raised active regions on the first semiconductor fins to remain unmerged, and raised active regions on the second semiconductor fins to become merged.

    Abstract translation: 通过控制半导体鳍片的表面上沉积的半导体材料的生长速率，可以在同一衬底上同时形成半导体鳍片上的合并和未熔合的凸起的有源区域。 在一个实施例中，生长速率缓冲掺杂剂可以通过成角度的离子注入注入第一半导体鳍片的侧壁表面上，在第二半导体鳍片被掩模层掩蔽的同时，其中需要延长生长速率。 在另一个实施例中，通过离子注入可以将生长速率增强掺杂剂注入到第二半导体鳍片的侧壁表面上，而第一半导体鳍片被掩蔽层掩蔽。 沉积的半导体材料的不同的生长速率可以使得第一半导体散热片上的凸起的有源区域保持不熔化，并且使第二半导体鳍片上的有源区域升高以合并。

    CONFORMAL DOPING FOR FINFET DEVICES
    19.
    发明申请
    CONFORMAL DOPING FOR FINFET DEVICES 有权
    FINFET器件的一致性掺杂

    公开(公告)号：US20150079773A1

    公开(公告)日：2015-03-19

    申请号：US14028517

    申请日：2013-09-16

    Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

    Inventor： Veeraraghavan S. Basker ,  Nathaniel Berliner ,  Hyun-Jin Cho ,  Johnathan Faltermeler ,  Kam-Leung Lee ,  Tenko Yamashita

    IPC: H01L21/18

    CPC classification number: H01L21/18 ,  H01L21/2236 ,  H01L21/2251 ,  H01L21/845 ,  H01L29/66803

    Abstract: A conformal doping process for FinFET devices on a semiconductor substrate which includes NFET fins and PFET fins. In a first exemplary embodiment, an N-type dopant composition is conformally deposited over the NFET fins and the PFET fins. The semiconductor substrate is annealed to drive in an N-type dopant from the N-type dopant composition into the NFET fins. A P-type dopant composition is conformally deposited over the NFET fins and the PFET fins. The semiconductor substrate is annealed to drive in a P-type dopant from the P-type dopant composition into the PFET fins. In a second exemplary embodiment, one of the NFETfins and PFET fins may be covered with a first dopant composition and then a second dopant composition may cover both the NFET fins and the PFET fins followed by an anneal to drive in both dopants.

    Abstract translation: 在包括NFET鳍片和PFET鳍片的半导体衬底上的FinFET器件的共形掺杂工艺。 在第一示例性实施例中，N型掺杂剂组合物共形沉积在NFET鳍片和PFET鳍片上。 将半导体衬底退火以将N型掺杂剂从N型掺杂剂组合物驱动到NFET鳍中。 P型掺杂剂组合物共形沉积在NFET鳍片和PFET鳍片上。 将半导体衬底退火以将P型掺杂剂从P型掺杂剂组合物驱动到PFET鳍中。 在第二示例性实施例中，可以用第一掺杂剂组合物覆盖NFET烯烃和PFET鳍中的一个，然后第二掺杂剂组合物可以覆盖NFET鳍和PFET鳍，然后进行退火以在两种掺杂剂中驱动。

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