公开(公告)号：US20170133373A1

公开(公告)日：2017-05-11

申请号：US14938499

申请日：2015-11-11

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Shyue Seng Tan ,  Kiok Boone Elgin Quek

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/0922 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L27/0924 ,  H01L29/66537 ,  H01L29/66803

Abstract: Integrated circuits including multiple gate devices with dual threshold voltages and methods for fabricating such integrated circuits are provided. An exemplary method for fabricating an integrated device includes providing a semiconductor fin structure overlying a semiconductor substrate. The semiconductor fin structure has a first sidewall, a second sidewall opposite the first sidewall, and an upper surface. The method includes forming a first gate along the first sidewall of the semiconductor fin structure with a first threshold voltage. Further, the method includes forming a second gate along the second sidewall of the semiconductor fin structure with a second threshold voltage different from the first threshold voltage.

公开(公告)号：US20170069753A1

公开(公告)日：2017-03-09

申请号：US14844522

申请日：2015-09-03

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Eng Huat Toh ,  Kiok Boone Elgin Quek

IPC: H01L29/78 ,  H01L21/283 ,  H01L21/02 ,  H01L21/306 ,  H01L29/08 ,  H01L29/06 ,  H01L29/10 ,  H01L29/36 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/7827 ,  H01L21/02636 ,  H01L21/283 ,  H01L21/30604 ,  H01L29/0657 ,  H01L29/083 ,  H01L29/0847 ,  H01L29/1041 ,  H01L29/36 ,  H01L29/4236 ,  H01L29/66356 ,  H01L29/66553 ,  H01L29/66666 ,  H01L29/66977 ,  H01L29/7391

Abstract: Integrated circuits including tunnel transistors and methods for fabricating such integrated circuits are provided. An exemplary method for fabricating an integrated device includes forming a lower source/drain region in and/or over a semiconductor substrate. The method forms a channel region overlying the lower source/drain region. The method also forms an upper source/drain region overlying the channel region. The method includes forming a gate structure beside the channel region.

Abstract translation: 提供了包括隧道晶体管的集成电路和用于制造这种集成电路的方法。 用于制造集成器件的示例性方法包括在半导体衬底内和/或之上形成下源/漏区。 该方法形成覆盖下部源极/漏极区域的沟道区域。 该方法还形成覆盖沟道区域的上部源极/漏极区域。 该方法包括在通道区域旁边形成栅极结构。

公开(公告)号：US20250142984A1

公开(公告)日：2025-05-01

申请号：US18384948

申请日：2023-10-30

Applicant: GlobalFoundries Singapore Pte. Ltd.

Inventor： Ping Zheng ,  Eng Huat Toh ,  Kiok Boone Elgin Quek

IPC: H01L31/107 ,  H01L31/0352 ,  H01L31/18

Abstract: Structures for a single-photon avalanche diode and methods of forming a structure for a single-photon avalanche diode. The structure comprises a semiconductor layer on a top surface of a semiconductor substrate, a light-absorbing layer on a first portion of the semiconductor layer, a dielectric layer on a second portion of the semiconductor layer, and a doped region in the semiconductor substrate adjacent to the semiconductor layer. The structure further comprises a deep trench isolation structure that penetrates through the dielectric layer and the second portion of the semiconductor layer to the doped region. The deep trench isolation structure includes a conductor layer and a dielectric liner, the dielectric liner includes a portion between the conductor layer and the semiconductor layer, and the conductor layer is connected to the first doped region.

公开(公告)号：US20250142983A1

公开(公告)日：2025-05-01

申请号：US18384915

申请日：2023-10-30

Applicant: GlobalFoundries Singapore Pte. Ltd.

Inventor： Ping Zheng ,  Eng Huat Toh ,  Kiok Boone Elgin Quek ,  Soh Yun Siah ,  Shiang Yang Ong

IPC: H01L31/107 ,  H01L21/762 ,  H01L31/18

Abstract: Structures for a single-photon avalanche diode and methods of forming a structure for a single-photon avalanche diode. The structure comprises a semiconductor layer on a semiconductor substrate, a cathode comprising a first doped region in the semiconductor substrate, and an anode comprising a second doped region adjacent to a top surface of the semiconductor layer. The structure further comprises a first trench isolation structure including a first conductor layer extending from the top surface of the semiconductor layer through the semiconductor layer to the first doped region. The first conductor layer of the first trench isolation structure is connected to the first doped region. The structure further comprises a second trench isolation structure adjacent to the first trench isolation structure. The second trench isolation structure includes a second conductor layer extending from the top surface of the semiconductor layer fully through the first doped region.

公开(公告)号：US12183754B2

公开(公告)日：2024-12-31

申请号：US17410025

申请日：2021-08-24

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Ping Zheng ,  Eng Huat Toh ,  Eric Linardy ,  Kiok Boone Elgin Quek

IPC: H01L27/146 ,  H01L31/107

Abstract: Structures for a single-photon avalanche diode and methods of forming a structure for a single-photon avalanche diode. The structure includes a semiconductor layer having a first well and a second well defining a p-n junction with the first well, and an interlayer dielectric layer on the semiconductor layer. A deep trench isolation region includes a conductor layer and a dielectric liner. The conductor layer penetrates through the semiconductor layer and the interlayer dielectric layer. The conductor layer has a first end, a second end, and a sidewall that connects the first end to the second end. The dielectric liner is arranged to surround the sidewall of the conductor layer. A metal feature is connected to the first end of the conductor layer.

公开(公告)号：US20230395619A1

公开(公告)日：2023-12-07

申请号：US18236484

申请日：2023-08-22

Applicant: GlobalFoundries Singapore Pte. Ltd.

Inventor： Ping Zheng ,  Eng Huat Toh ,  Kiok Boone Elgin Quek ,  Kien Seen Daniel Chong ,  Jing Hua Michelle Tng

IPC: H01L27/146

CPC classification number: H01L27/1461 ,  H01L27/14645 ,  H01L27/1463 ,  H01L27/14689 ,  H01L27/14627 ,  H01L31/107

Abstract: Structures for a single-photon avalanche diode and methods of forming a structure for a single-photon avalanche diode. The structure includes a semiconductor substrate having a top surface, a semiconductor layer on the top surface of the semiconductor substrate, a light-absorbing layer on a portion of the semiconductor layer, and a doped region in the portion of the semiconductor layer. The doped region is positioned in the portion of the semiconductor layer adjacent to the light-absorbing layer.

公开(公告)号：US20230131505A1

公开(公告)日：2023-04-27

申请号：US17507213

申请日：2021-10-21

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Eric Linardy ,  Eng Huat Toh ,  Ping Zheng ,  Kiok Boone Elgin Quek

IPC: H01L27/146

Abstract: Structures for a photodetector and methods of forming a structure for a photodetector. The structure includes a semiconductor layer having a p-n junction and a deep trench isolation region extending through the semiconductor layer. The deep trench isolation region includes first layers and second layers that alternate with the first layers to define a Bragg mirror. The first layers contain a first material having a first refractive index, and the second layers contain a second material having a second refractive index that is greater than the first refractive index.

公开(公告)号：US11437392B2

公开(公告)日：2022-09-06

申请号：US16940586

申请日：2020-07-28

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Yongshun Sun ,  Eng Huat Toh ,  Shyue Seng Tan ,  Kiok Boone Elgin Quek

IPC: H01L27/11568 ,  H01L29/792

Abstract: An illustrative device disclosed herein includes a first memory cell comprising a first memory gate positioned above an upper surface of a semiconductor substrate and a second memory cell comprising a second memory gate positioned above the upper surface of the semiconductor substrate. In this example, the device also includes a conductive select gate structure positioned above the upper surface of the semiconductor substrate between the first and second memory gates, wherein the conductive select gate structure is shared by the first and second memory cells.

公开(公告)号：US11309324B2

公开(公告)日：2022-04-19

申请号：US16940522

申请日：2020-07-28

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Yongshun Sun ,  Eng Huat Toh ,  Shyue Seng Tan ,  Kiok Boone Elgin Quek

IPC: H01L27/11568 ,  H01L29/423 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11521 ,  H01L29/788 ,  H01L21/28 ,  H01L23/535

Abstract: An illustrative device disclosed herein includes a first memory cell comprising a first memory gate positioned above an upper surface of a semiconductor substrate and a second memory cell comprising a second memory gate positioned above the upper surface of the semiconductor substrate. In this example, the device also includes a conductive word line structure positioned above the upper surface of the semiconductor substrate between the first and second memory gates, wherein the conductive word line structure is shared by the first and second memory cells.

公开(公告)号：US11158643B2

公开(公告)日：2021-10-26

申请号：US16695725

申请日：2019-11-26

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Lanxiang Wang ,  Shyue Seng Tan ,  Kiok Boone Elgin Quek ,  Xinshu Cai ,  Eng Huat Toh

IPC: H01L27/11519 ,  H01L27/11521

Abstract: Structures for a non-volatile memory bit cell and methods of forming a structure for a non-volatile memory bit cell. A field-effect transistor has a channel region and a first gate electrode positioned over the channel region. A capacitor includes a second gate electrode that is coupled to the first gate electrode to define a floating gate. The first gate electrode has a non-rectangular shape.