公开(公告)号：US09905282B1

公开(公告)日：2018-02-27

申请号：US15608407

申请日：2017-05-30

申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

发明人： Wanbing Yi ,  Curtis Chun-I Hsieh ,  Soh Yun Siah ,  Juan Boon Tan

IPC分类号： G11C11/15 ,  G11C11/16 ,  H01F10/32 ,  H01F41/30 ,  H01L27/22 ,  H01L43/12

CPC分类号： G11C11/16 ,  H01F10/3254 ,  H01F41/303 ,  H01L27/222 ,  H01L43/12

摘要： Methods of fabricating a dome-shaped MTJ TE and the resulting devices are provided. Embodiments include forming a MRAM stack having a laterally separated MTJ structures and the MRAM and a logic stack each having a SiN layer; forming first trenches through the MRAM stack to a portion of the SiN layer above an MTJ structure; forming second trenches through the SiN layer fully landing on an upper portion of the MTJ structures and removing the SiN layer of the logic stack; forming a TaN layer over the MRAM and logic stack; removing portions of the TaN layer on opposite sides of the MTJ structures and therebetween; forming an oxide layer over the MRAM and logic stacks; and forming vias through the oxide layer of the MRAM stack down the TaN layer above MTJ structures and a via through the logic stack.

公开(公告)号：US09793208B2

公开(公告)日：2017-10-17

申请号：US14869963

申请日：2015-09-29

申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

发明人： Haifeng Sheng ,  Juan Boon Tan ,  Wanbing Yi ,  Daxiang Wang ,  Soh Yun Siah

IPC分类号： H01L23/525 ,  H01L21/02 ,  H01L21/3065 ,  H01L23/62 ,  H01L21/3213 ,  H01L27/07 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/02

CPC分类号： H01L23/5256 ,  H01L21/32136 ,  H01L21/76802 ,  H01L21/823892 ,  H01L23/62 ,  H01L27/0255 ,  H01L27/0727

摘要： A semiconductor device with a temporary discharge path. During back-end-of-line (BEOL), the temporary discharge path discharges a plasma charge collected in a device well, such as a floating p-type well. After processing, the temporary discharge path is rendered non-function, enabling the device to function properly.

公开(公告)号：US09111866B2

公开(公告)日：2015-08-18

申请号：US13788174

申请日：2013-03-07

申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

发明人： Yu Chen ,  Huajun Liu ,  Siow Lee Chwa ,  Soh Yun Siah ,  Yanxia Shao ,  Yoke Leng Lim

IPC分类号： H01L29/788 ,  H01L21/28 ,  H01L27/115 ,  H01L29/423

CPC分类号： H01L27/11521 ,  H01L21/0332 ,  H01L21/28273 ,  H01L21/3213 ,  H01L27/11568 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42344 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66825

摘要： Fabrication of a slim split gate cell and the resulting device are disclosed. Embodiments include forming a first gate on a substrate, the first gate having an upper surface and a hard-mask covering the upper surface, forming an interpoly isolation layer on side surfaces of the first gate and the hard-mask, forming a second gate on one side of the first gate, with an uppermost point of the second gate below the upper surface of the first gate, removing the hard-mask, forming spacers on exposed vertical surfaces, and forming a salicide on exposed surfaces of the first and second gates.

摘要翻译： 公开了一种细长分裂栅极电池的制造和所得到的器件。 实施例包括在基板上形成第一栅极，第一栅极具有上表面和覆盖上表面的硬掩模，在第一栅极和硬掩模的侧表面上形成间隔隔离层，形成第二栅极 第一栅极的一侧，第二栅极的最上部点在第一栅极的上表面下方，去除硬掩模，在暴露的垂直表面上形成间隔物，并在第一和第二栅极的暴露表面上形成硅化物 。

公开(公告)号：US08957523B2

公开(公告)日：2015-02-17

申请号：US13737957

申请日：2013-01-10

申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

发明人： Fan Zhang ,  Wei Shao ,  Juan Boon Tan ,  Yeow Kheng Lim ,  Mahesh Bhatkar ,  Soh Yun Siah

IPC分类号： H01L23/52 ,  H01L23/00 ,  H01L23/538 ,  H01L23/58

CPC分类号： H01L23/562 ,  H01L23/528 ,  H01L23/5384 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device is disclosed. The semiconductor device includes a substrate comprises a plurality of metal layers. The semiconductor device also includes dielectric posts disposed in the metal layers. The density of the dielectric posts in the metal layers is equal to about 15-25%.

摘要翻译： 公开了一种半导体器件。 半导体器件包括包括多个金属层的衬底。 半导体器件还包括设置在金属层中的电介质柱。 金属层中的电介质柱的密度等于约15-25％。

公开(公告)号：US10439129B2

公开(公告)日：2019-10-08

申请号：US15874077

申请日：2018-01-18

申请人： GLOBALFOUNDRIES Singapore Pte Ltd

发明人： Dimitri Houssameddine ,  Chenchen Jacob Wang ,  Bin Liu ,  Soh Yun Siah

IPC分类号： H01L43/02 ,  H01L23/552 ,  H01L27/22

摘要： One illustrative integrated circuit (IC) product disclosed herein includes an MRAM cell, the MRAM cell having an outer perimeter, wherein the MRAM cell comprises a bottom electrode, a top electrode and an MTJ (Magnetic Tunnel Junction) element positioned above the bottom electrode and below the top electrode. In this example, the IC product also includes an insulating material positioned around the outer perimeter of the MRAM cell and a conductive sidewall spacer comprised of a metal-containing shielding material positioned around the outer perimeter of the MRAM cell, wherein the insulating material is positioned between the conductive sidewall spacer and the MRAM cell.

公开(公告)号：US10224338B2

公开(公告)日：2019-03-05

申请号：US15490329

申请日：2017-04-18

申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

发明人： Soh Yun Siah

IPC分类号： H01L27/11568 ,  H01L21/02 ,  H01L27/11521 ,  H01L21/3205

摘要： A method of forming a memory device with a dielectric blocking layer and selective silicidation and the resulting device are provided. Embodiments include forming a memory stack on a substrate; forming a conformal insulating layer over sidewalls and an upper surface of the memory stack and the substrate; forming an interpoly dielectric structure adjacent to each sidewall of the insulating layer; forming a conformal polysilicon silicon layer over the insulating layer and interpoly dielectric structures; forming an optical planarization layer over the polysilicon layer; planarizing the optical planarization and polysilicon layers down to the memory stack; forming a dielectric blocking layer over the memory stack and substrate; forming a patterning stack over the dielectric blocking layer, the patterning stack covering a portion of the memory stack; and removing the dielectric blocking, optical planarization, and polysilicon layers on opposite sides of the patterning stack.

公开(公告)号：US20180076128A1

公开(公告)日：2018-03-15

申请号：US15263830

申请日：2016-09-13

申请人： Globalfoundries Singapore Pte. Ltd.

发明人： Haifeng Sheng ,  Shifeng Zhao ,  Juan Boon Tan ,  Soh Yun Siah

IPC分类号： H01L23/522 ,  H01L23/528 ,  H01L27/115 ,  H01L21/768

CPC分类号： H01L23/5225 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/115

摘要： Integrated circuits and methods of forming the same are provided herein. In an embodiment, an integrated circuit includes a semiconductor substrate that has an isolated well. A multilayer metallization stack overlies the semiconductor substrate. The multilayer metallization stack includes a metal layer, a functional via, and a dummy metal feature. The metal layer includes a first line in electrical communication with the isolated well through a contact. The functional via is in electrical communication with the first line and the contact. The dummy metal feature is in electrical communication with the functional via.

公开(公告)号：US09236391B2

公开(公告)日：2016-01-12

申请号：US14732867

申请日：2015-06-08

申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

发明人： Yu Chen ,  Huajun Liu ,  Siow Lee Chwa ,  Soh Yun Siah ,  Yanxia Shao ,  Yoke Leng Lim

IPC分类号： H01L29/00 ,  H01L27/115 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L21/033 ,  H01L21/3213

CPC分类号： H01L27/11521 ,  H01L21/0332 ,  H01L21/28273 ,  H01L21/3213 ,  H01L27/11568 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42344 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66825

摘要： Fabrication of a slim split gate cell and the resulting device are disclosed. Embodiments include forming a first gate on a substrate, the first gate having an upper surface and a hard-mask covering the upper surface, forming an interpoly isolation layer on side surfaces of the first gate and the hard-mask, forming a second gate on one side of the first gate, with an uppermost point of the second gate below the upper surface of the first gate, removing the hard-mask, forming spacers on exposed vertical surfaces, and forming a salicide on exposed surfaces of the first and second gates.