公开(公告)号：US20190229094A1

公开(公告)日：2019-07-25

申请号：US16333020

申请日：2016-09-13

Applicant: Google LLC

Inventor： Theodore Charles White

IPC: H01L25/065 ,  H01P7/08 ,  H01L25/00 ,  H01L23/00 ,  H01L23/48 ,  H01L23/532 ,  H01L23/66 ,  G06N10/00

Abstract: The proposed device includes a first chip (102) comprising a superconducting quantum bit and a second chip (104) bonded to the first chip, the second chip including a substrate (108) having first and second opposing surfaces. The first surface (101) facing the first chip includes a layer (105) of superconductor material which includes a first circuit element. The second chip further includes a second layer (107) on the second surface (103) which includes a second circuit element, and a through connector (109) that extends from the first surface to the second surface and electrically connects a portion of the superconductor material layer to the second circuit element.

公开(公告)号：US11955465B2

公开(公告)日：2024-04-09

申请号：US18103227

申请日：2023-01-30

Applicant: Google LLC

Inventor： Theodore Charles White

IPC: H01L23/538 ,  G06N10/00 ,  H01L21/02 ,  H01L23/00 ,  H01L23/48 ,  H01L23/532 ,  H01L23/66 ,  H01L25/00 ,  H01L25/065 ,  H01P7/08 ,  H10N69/00

CPC classification number: H01L25/0657 ,  G06N10/00 ,  H01L23/481 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/53285 ,  H01L23/66 ,  H01L24/05 ,  H01L24/13 ,  H01L25/50 ,  H01P7/086 ,  H10N69/00 ,  H01L2223/6611 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05179 ,  H01L2224/13109 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13164 ,  H01L2224/13179 ,  H01L2224/13183 ,  H01L2224/81409 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/04941

Abstract: A device includes: a first chip including a qubit; and a second chip bonded to the first chip, the second chip including a substrate including first and second opposing surfaces, the first surface facing the first chip, wherein the second chip includes a single layer of superconductor material on the first surface of the substrate, the single layer of superconductor material including a first circuit element. The second chip further includes a second layer on the second surface of the substrate, the second layer including a second circuit element. The second chip further includes a through connector that extends from the first surface of the substrate to the second surface of the substrate and electrically connects a portion of the single layer of superconducting material to the second circuit element.

公开(公告)号：US20230225223A1

公开(公告)日：2023-07-13

申请号：US18117918

申请日：2023-03-06

Applicant: Google LLC

Inventor： Brian James Burkett ,  Ofer Naaman ,  Anthony Edward Megrant ,  Theodore Charles White

IPC: H01L39/22 ,  G06N10/00

CPC classification number: H10N60/0912 ,  G06N10/00 ,  H10N60/12 ,  H10N60/805

Abstract: Methods, systems and apparatus for forming Josephson junctions with reduced stray inductance. In one aspect, a device includes a substrate; a first superconductor layer on the substrate; an insulator layer on the first superconductor layer; a second superconductor layer on the insulator layer, wherein the first superconductor layer, the insulator layer, and the second superconductor layer form a superconductor tunnel junction; and a third superconductor layer directly on a surface of the first superconductor layer and directly on a surface of the second superconductor layer to provide a first contact to the superconducting tunnel junction and a second contact to the superconductor tunnel junction, respectively.

公开(公告)号：US11450938B2

公开(公告)日：2022-09-20

申请号：US16462263

申请日：2017-09-13

Applicant: Google LLC

Inventor： Theodore Charles White ,  Anthony Edward Megrant

IPC: G06N10/00 ,  H01L39/24 ,  H01P7/08 ,  H01L27/18

Abstract: A device includes: a substrate; a first superconductor layer on the substrate, the first superconductor layer having a first kinetic inductance; and a second superconductor layer on the first superconductor layer, the second superconductor layer having a second kinetic inductance that is lower than the first kinetic inductance, in which the second superconductor layer covers the first superconductor layer such that the second superconductor layer and the first superconductor layer have a same footprint, with the exception of at least a first region where the second superconductor layer is omitted so that the first superconductor layer and the second superconductor layer form a circuit element having a predetermined circuit parameter.

公开(公告)号：US20190341668A1

公开(公告)日：2019-11-07

申请号：US16462263

申请日：2017-09-13

Applicant: Google LLC

Inventor： Theodore Charles White ,  Anthony Edward Megrant

IPC: H01P7/08 ,  G06N10/00 ,  H01L39/24

Abstract: A device includes: a substrate; a first superconductor layer on the substrate, the first superconductor layer having a first kinetic inductance; and a second superconductor layer on the first superconductor layer, the second superconductor layer having a second kinetic inductance that is lower than the first kinetic inductance, in which the second superconductor layer covers the first superconductor layer such that the second superconductor layer and the first superconductor layer have a same footprint, with the exception of at least a first region where the second superconductor layer is omitted so that the first superconductor layer and the second superconductor layer form a circuit element having a predetermined circuit parameter.

公开(公告)号：US20190229690A1

公开(公告)日：2019-07-25

申请号：US16333122

申请日：2016-09-15

Applicant: Google LLC

Inventor： Theodore Charles White ,  Julian Shaw Kelly

IPC: H03F19/00 ,  G06N10/00 ,  H03H11/04 ,  H03K19/195

Abstract: A quantum computing devices includes: a qubit; a readout device coupled to the qubit, the readout device including a frequency filter having a filter frequency range; and an amplifier device coupled to the readout device, in which the amplifier device is configured to amplify a measurement signal from the readout device upon receiving a pump signal having a pump frequency that is outside of the filter frequency range of the frequency filter.

公开(公告)号：US20250068952A1

公开(公告)日：2025-02-27

申请号：US18456208

申请日：2023-08-25

Applicant: Google LLC

Inventor： Nicholas Reinhard Zobrist ,  Kevin Chenghao Miao ,  Alex Opremcak ,  Ofer Naaman ,  Theodore Charles White ,  Daniel Sank

IPC: G06N10/40

Abstract: A quantum computing system includes a cryogenic chamber and an integrated circuit located in the chamber. The integrated circuit includes a substrate, a qubit formed on the substrate, and a dissipative element that is formed on the substrate and coupled to the qubit. When the qubit is tuned to a first flux value, the integrated circuit is enabled to perform quantum-computation operations on a set of quantum states of the qubit. The quantum states include a ground state and an excited state. When the qubit is tuned to a second flux value, the qubit is enabled to transfer energy associated with the excited state from the qubit to the dissipative element. Upon the energy transfer, the qubit is transitioned to the ground state. The dissipative element is enabled to dissipate the transferred energy to a portion of the substrate.

公开(公告)号：US12239027B2

公开(公告)日：2025-02-25

申请号：US18117918

申请日：2023-03-06

Applicant: Google LLC

Inventor： Brian James Burkett ,  Ofer Naaman ,  Anthony Edward Megrant ,  Theodore Charles White

IPC: H10N60/01 ,  G06N10/00 ,  H10N60/12 ,  H10N60/80

Abstract: Methods, systems and apparatus for forming Josephson junctions with reduced stray inductance. In one aspect, a device includes a substrate; a first superconductor layer on the substrate; an insulator layer on the first superconductor layer; a second superconductor layer on the insulator layer, wherein the first superconductor layer, the insulator layer, and the second superconductor layer form a superconductor tunnel junction; and a third superconductor layer directly on a surface of the first superconductor layer and directly on a surface of the second superconductor layer to provide a first contact to the superconducting tunnel junction and a second contact to the superconductor tunnel junction, respectively.

公开(公告)号：US20240194661A1

公开(公告)日：2024-06-13

申请号：US18080729

申请日：2022-12-13

Applicant: Google LLC

Inventor： Zhimin Jamie Yao ,  Michael C. Hamilton ,  Marissa Giustina ,  Brian James Burkett ,  Theodore Charles White ,  Ofer Naaman

IPC: H01L25/00 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L24/81 ,  H01L24/13 ,  H01L2224/13109 ,  H01L2224/81815

Abstract: A method includes providing a first chip having a circuit element layer stack, the circuit element layer stack including a plurality of circuit elements distributed across a plurality of layers. The circuit element layer stack has a sacrificial material filling a space between the plurality of circuit elements in the plurality of layers and a coherent device layer disposed on the circuit element layer stack. The method includes removing the sacrificial material.

公开(公告)号：US20240194532A1

公开(公告)日：2024-06-13

申请号：US18080715

申请日：2022-12-13

Applicant: Google LLC

Inventor： Zhimin Jamie Yao ,  Michael C. Hamilton ,  Marissa Giustina ,  Brian James Burkett ,  Theodore Charles White ,  Ofer Naaman

IPC: H01L21/822 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L23/00 ,  H01L25/07

CPC classification number: H01L21/8221 ,  H01L21/02505 ,  H01L21/02598 ,  H01L21/31127 ,  H01L21/7688 ,  H01L24/16 ,  H01L24/29 ,  H01L25/074 ,  B82Y10/00

Abstract: A method includes providing a first chip having a circuit element layer stack, the circuit element layer stack including a plurality of circuit elements distributed across a plurality of layers. The circuit element layer stack has a sacrificial material filling a space between the plurality of circuit elements in the plurality of layers and a coherent device layer disposed on the circuit element layer stack. The method includes removing the sacrificial material.