公开(公告)号：US20080042280A1

公开(公告)日：2008-02-21

申请号：US11769736

申请日：2007-06-28

申请人： Mou-Shiung Lin ,  Jin-Yuan Lee

发明人： Mou-Shiung Lin ,  Jin-Yuan Lee

IPC分类号： H01L23/48

CPC分类号： H01L24/11 ,  H01L23/5227 ,  H01L23/53238 ,  H01L23/53252 ,  H01L24/05 ,  H01L24/06 ,  H01L24/12 ,  H01L24/16 ,  H01L24/28 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/94 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05084 ,  H01L2224/05553 ,  H01L2224/05568 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/1147 ,  H01L2224/1308 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/13171 ,  H01L2224/13173 ,  H01L2224/13176 ,  H01L2224/13181 ,  H01L2224/13183 ,  H01L2224/16 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48463 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48669 ,  H01L2224/48747 ,  H01L2224/48755 ,  H01L2224/48764 ,  H01L2224/48769 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/73204 ,  H01L2224/838 ,  H01L2224/85201 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/0665 ,  H01L2924/0781 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2924/01032 ,  H01L2924/01031 ,  H01L2224/48869 ,  H01L2224/48744 ,  H01L2224/05552

摘要： A semiconductor chip structure includes a semiconductor substrate, an circuit structure, a passivation layer, a first adhesion/barrier layer, a metal cap and a metal layer. The semiconductor substrate has multiple electric devices located on a surface layer of a surface of the substrate. The circuit structure had multiple circuit layers electrically connecting with each other and electrically connecting with the electric devices. One of the circuit layers has multiple pads. The passivation layer is located on the circuit structure and has multiple openings penetrating through the passivation layer. The openings expose the pads. The first adhesion/barrier layer is over the pads and the passivation layer. The metal cap is located on the first adhesion/barrier layer and the passivation layer. The metal layer is on the metal layer.

摘要翻译： 半导体芯片结构包括半导体衬底，电路结构，钝化层，第一粘附/阻挡层，金属帽和金属层。 半导体衬底具有位于衬底表面的表面层上的多个电子器件。 电路结构具有彼此电连接并与电气装置电连接的多个电路层。 其中一个电路层具有多个焊盘。 钝化层位于电路结构上，具有贯穿钝化层的多个开口。 开口露出垫。 第一粘附/阻挡层在焊盘和钝化层之上。 金属盖位于第一粘附/阻挡层和钝化层上。 金属层在金属层上。

公开(公告)号：US20070023919A1

公开(公告)日：2007-02-01

申请号：US11383762

申请日：2006-05-17

申请人： Mou-Shiung Lin ,  Hsin-Jung Lo ,  Chiu-Ming Chou ,  Chien-Kang Chou ,  Ke-Hung Chen

发明人： Mou-Shiung Lin ,  Hsin-Jung Lo ,  Chiu-Ming Chou ,  Chien-Kang Chou ,  Ke-Hung Chen

IPC分类号： H01L23/48

CPC分类号： H01L24/11 ,  H01L23/525 ,  H01L24/12 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/05672 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/0603 ,  H01L2224/06102 ,  H01L2224/1147 ,  H01L2224/11902 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/13173 ,  H01L2224/13176 ,  H01L2224/13183 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/10329 ,  H01L2924/12043 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00014 ,  H01L2924/013

摘要： A bonding pad structure is fabricated on an integrated circuit (IC) substrate having at least a contact layer on its top surface. A passivation layer covers the top surface of the IC substrate and the contact layer. The passivation layer has an opening exposing a portion of the contact layer. An electrically conductive adhesion/barrier layer directly is bonded to the contact layer. The electrically conductive adhesion/barrier layer extends to a top surface of the passivation layer. A bonding metal layer is stacked on the electrically conductive adhesion/barrier layer.

摘要翻译： 在具有至少在其顶表面上的接触层的集成电路（IC）衬底上制造焊盘结构。 钝化层覆盖IC基板的顶表面和接触层。 钝化层具有露出接触层的一部分的开口。 导电性粘合/阻挡层直接接合到接触层。 导电粘合/阻挡层延伸到钝化层的顶表面。 接合金属层层叠在导电性粘接/阻挡层上。

公开(公告)号：US12086689B1

公开(公告)日：2024-09-10

申请号：US18229071

申请日：2023-08-01

申请人： Google LLC

发明人： Julian Shaw Kelly ,  Evan Jeffrey

IPC分类号： G06N10/40 ,  B82Y10/00 ,  G06N10/00 ,  H01L23/00 ,  H01L25/04 ,  H01L25/065 ,  H01L25/07 ,  H01L25/075 ,  H10N69/00

CPC分类号： G06N10/40 ,  G06N10/00 ,  H01L24/13 ,  H01L24/16 ,  B82Y10/00 ,  H01L25/043 ,  H01L25/0657 ,  H01L25/074 ,  H01L25/0756 ,  H01L2224/13109 ,  H01L2224/13116 ,  H01L2224/13164 ,  H01L2224/13179 ,  H01L2224/13183 ,  H01L2224/13644 ,  H01L2225/06513 ,  H01L2225/06531 ,  H01L2225/06537 ,  H10N69/00

摘要： A device includes: a first chip including a plurality of qubits arranged in an array on a first side of the first chip, in which the array includes a plurality of qubit rows and a plurality of qubit columns, in which the plurality of qubits includes a first qubit row including two or more qubits and a second qubit row including two or more qubits, and in which the second qubit row is directly adjacent to the first qubit row; a second chip bonded to the first chip, in which the second chip has a first side that faces the first side of the first chip; a plurality of qubit control elements; a plurality of qubit readout resonators; and a plurality of qubit readout transmission lines.

公开(公告)号：US20180366634A1

公开(公告)日：2018-12-20

申请号：US16062064

申请日：2015-12-30

申请人： Joshua Yousouf MUTUS ,  Anthony Erik LUCERO ,  GOOGLE LLC

发明人： Joshua Yousouf Mutus ,  Erik Anthony LUCERO

IPC分类号： H01L39/04 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC分类号： H01L39/045 ,  H01L23/49816 ,  H01L23/49888 ,  H01L24/03 ,  H01L24/05 ,  H01L24/10 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L27/18 ,  H01L2224/0345 ,  H01L2224/0362 ,  H01L2224/0381 ,  H01L2224/03826 ,  H01L2224/0384 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05025 ,  H01L2224/05124 ,  H01L2224/05179 ,  H01L2224/05186 ,  H01L2224/05564 ,  H01L2224/05568 ,  H01L2224/05669 ,  H01L2224/05684 ,  H01L2224/05686 ,  H01L2224/1145 ,  H01L2224/1181 ,  H01L2224/13023 ,  H01L2224/13109 ,  H01L2224/13116 ,  H01L2224/13164 ,  H01L2224/13179 ,  H01L2224/13183 ,  H01L2224/16145 ,  H01L2224/81013 ,  H01L2224/81193 ,  H01L2224/81201 ,  H01L2224/81409 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/10329 ,  H01L2924/20102 ,  H01L2924/00014 ,  H01L2924/04941

摘要： A device (100) includes a first chip (104) having a first circuit element (112), a first interconnect pad (116) in electrical contact (118) with the first circuit element, and a barrier layer (120) on the first interconnect pad, a superconducting bump bond (106) on the barrier layer, and a second chip (102) joined to the first chip by the superconducting bump bond, the second chip having a quantum circuit element (108), in which the superconducting bump bond provides an electrical connection between the first circuit element and the quantum circuit element.

公开(公告)号：US09865648B2

公开(公告)日：2018-01-09

申请号：US14109604

申请日：2013-12-17

申请人： D-Wave Systems Inc.

发明人： Paul I. Bunyk

IPC分类号： H01L27/18 ,  H01L39/04 ,  H01L23/00 ,  H01L39/24 ,  G01R31/28

CPC分类号： H01L27/18 ,  G01R31/2884 ,  G01R31/2891 ,  H01L24/05 ,  H01L24/13 ,  H01L24/81 ,  H01L39/045 ,  H01L39/24 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05023 ,  H01L2224/05179 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/13007 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13163 ,  H01L2224/13176 ,  H01L2224/13183 ,  H01L2224/13562 ,  H01L2224/1357 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/13611 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2924/15787 ,  H01L2924/35121 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01076 ,  H01L2224/81 ,  H01L2924/00

摘要： Superconductive interconnection structures providing continuous, uninterrupted superconducting signal paths between a superconducting chip and a superconducting chip carrier are described. The superconductive interconnection structures employ superconducting solder bumps and pillars of Under Bump Metal (“UBM”). The superconductive interconnection structures are employed in a two-stage solder bumping process in which the superconducting chip is first bonded to a testing module for screening and then bonded to a chip packaging module for operation. Either the testing module or the chip packaging module, or both, may include a multi-chip module for carrying multiple superconducting chips simultaneously.

公开(公告)号：US20170154850A1

公开(公告)日：2017-06-01

申请号：US15143950

申请日：2016-05-02

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Min-Feng Kao ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Hsun-Ying Huang

IPC分类号： H01L23/538 ,  H01L21/768 ,  H01L23/31 ,  H01L23/528 ,  H01L23/00

CPC分类号： H01L23/5384 ,  H01L21/6835 ,  H01L21/76804 ,  H01L21/76832 ,  H01L21/76883 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/481 ,  H01L23/522 ,  H01L23/525 ,  H01L23/5283 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/02313 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13183 ,  H01L2224/16227 ,  H01L2224/16245 ,  H01L2224/81005 ,  H01L2224/81815 ,  H01L2924/01013 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01047

摘要： In some embodiments, the present disclosure relates to an integrated chip (IC) having a back-side through-silicon-via (BTSV) with a direct physical connection between a metal interconnect layer and a back-side conductive bond pad. The IC has metal interconnect layers arranged within an inter-level dielectric structure disposed onto a front-side of a substrate. A dielectric layer is arranged along a back-side of the substrate, and a conductive bond pad is arranged over the dielectric layer. A BTSV extends from one of the metal interconnect layers through the substrate and the dielectric layer to the conductive bond pad. A conductive bump is arranged onto the conductive bond pad, which has a substantially planar lower surface extending from over the BTSV to below the conductive bump. Directly connecting the conductive bond pad to the BTSV reduces a size of the conductive bond thereby improving a routing capability of the conductive bond pad.

公开(公告)号：US11770982B1

公开(公告)日：2023-09-26

申请号：US17397015

申请日：2021-08-09

申请人： Rigetti & Co, LLC

发明人： Jayss Daniel Marshall ,  Chih-Yang Li ,  Biswajit Sur ,  Nagesh Vodrahalli ,  Mehrnoosh Vahidpour ,  William Austin O'Brien, IV ,  Andrew Joseph Bestwick ,  Chad Tyler Rigetti ,  James Russell Renzas

IPC分类号： H10N60/80 ,  H01L23/00 ,  G06N10/00 ,  H10N60/85 ,  H10N60/01

CPC分类号： H10N60/805 ,  G06N10/00 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H10N60/0156 ,  H10N60/0912 ,  H10N60/85 ,  H01L2224/1146 ,  H01L2224/11452 ,  H01L2224/1318 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/13109 ,  H01L2224/13124 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13179 ,  H01L2224/13183 ,  H01L2224/13184 ,  H01L2224/16238 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2924/1432

摘要： In a general aspect, an integrated quantum circuit includes a first substrate and a second substrate. The first substrate includes a first surface and a recess formed in the first substrate along the first surface. The recess has a recess surface and is configured to enclose a quantum circuit element. The first substrate includes a first electrically-conductive layer disposed on the first surface and covering at least a portion of the recess surface. The first electrically-conductive layer includes a first superconducting material. The second substrate includes a second surface and a quantum circuit element. The second substrate includes a second electrically-conductive layer on the second surface that includes a second superconducting material. The first substrate is adjacent the second substrate to enclose the quantum circuit device within the recess. The first electrically-conductive layer of the first substrate is electrically-coupled to the second electrically-coupled layer of the second substrate.

公开(公告)号：US08816499B2

公开(公告)日：2014-08-26

申请号：US13826694

申请日：2013-03-14

申请人： Samsung Electronics Co., Ltd.

发明人： Ju-il Choi ,  Jeong-Woo Park ,  Jeonggi Jin ,  Yeun-Sang Park

IPC分类号： H01L23/488 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L24/12 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05557 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/10145 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13012 ,  H01L2224/13013 ,  H01L2224/13014 ,  H01L2224/13017 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/13084 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13164 ,  H01L2224/13166 ,  H01L2224/13169 ,  H01L2224/13173 ,  H01L2224/13176 ,  H01L2224/13178 ,  H01L2224/13183 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2924/01024 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2224/05552

摘要： Provided are electrical interconnections and methods for fabricating the same. The electrical interconnection may include a substrate including a bonding pad, a solder ball electrically connected to the bonding pad, a solder supporter on the bonding pad, a portion of the solder ball filling the solder supporter, and a metal layer between the bonding pad and the solder supporter, the metal layer having an ionization tendency lower than the bonding pad.

摘要翻译： 提供电互连及其制造方法。 电互连可以包括：衬底，其包括接合焊盘，与接合焊盘电连接的焊球，焊盘上的焊料支撑体，填充焊料支撑体的焊球的一部分，以及焊接垫和 所述焊料支撑体，所述金属层的电离倾向低于所述接合焊盘。

公开(公告)号：US08749021B2

公开(公告)日：2014-06-10

申请号：US11964015

申请日：2007-12-25

申请人： Mou-Shiung Lin ,  Gu-Yeon Wei

发明人： Mou-Shiung Lin ,  Gu-Yeon Wei

IPC分类号： H01L27/08 ,  H01L27/11 ,  H01L29/00 ,  H01L23/58 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H02M3/00 ,  H01L23/49555 ,  H01L23/49575 ,  H01L23/5227 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L25/16 ,  H01L27/0605 ,  H01L2224/02166 ,  H01L2224/0231 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05548 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/0558 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/05669 ,  H01L2224/05673 ,  H01L2224/05676 ,  H01L2224/05683 ,  H01L2224/0603 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/11901 ,  H01L2224/11912 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/13173 ,  H01L2224/13176 ,  H01L2224/13183 ,  H01L2224/16 ,  H01L2224/16245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01031 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/3011 ,  H01L2924/01049 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2224/45099 ,  H01L2924/00012

摘要： The present invention reveals a semiconductor chip structure and its application circuit network, wherein the switching voltage regulator or converter is integrated with a semiconductor chip by chip fabrication methods, so that the semiconductor chip has the ability to regulate voltage within a specific voltage range. Therefore, when many electrical devices of different working voltages are placed on a Printed Circuit Board (PCB), only a certain number of semiconductor chips need to be constructed. Originally, in order to account for the different demands in voltage, power supply units of different output voltages, or a variety of voltage regulators need to be added. However, using the built-in voltage regulator or converter, the voltage range can be immediately adjusted to that which is needed. This improvement allows for easier control of electrical devices of different working voltages and decreases response time of electrical devices.

摘要翻译： 本发明揭示了半导体芯片结构及其应用电路网络，其中开关电压调节器或转换器通过芯片制造方法与半导体芯片集成，使得半导体芯片具有在特定电压范围内调节电压的能力。 因此，当印刷电路板（PCB）上放置许多不同工作电压的电气设备时，只需要构建一定数量的半导体芯片。 最初，为了解决电压的不同要求，需要增加不同输出电压的电源单元或各种电压调节器。 然而，使用内置的电压调节器或转换器，电压范围可以立即调整到所需的电压范围。 这种改进允许更容易地控制不同工作电压的电气设备并减少电气设备的响应时间。

公开(公告)号：US20070205520A1

公开(公告)日：2007-09-06

申请号：US11681219

申请日：2007-03-02

申请人： Chien-Kang Chou ,  Chiu-Ming Chou ,  Li-Ren Lin ,  Hsin-Jung Lo

发明人： Chien-Kang Chou ,  Chiu-Ming Chou ,  Li-Ren Lin ,  Hsin-Jung Lo

IPC分类号： H01L23/48

CPC分类号： H01L24/12 ,  H01L23/3157 ,  H01L23/4985 ,  H01L23/66 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04073 ,  H01L2224/05024 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05558 ,  H01L2224/05559 ,  H01L2224/05568 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/06102 ,  H01L2224/1147 ,  H01L2224/11902 ,  H01L2224/11912 ,  H01L2224/13022 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/13173 ,  H01L2224/13176 ,  H01L2224/13183 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/14505 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4807 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/48844 ,  H01L2224/48855 ,  H01L2224/73204 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06579 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01007 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/12044 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

摘要： A chip package includes a semiconductor substrate, a first metal pad over the semiconductor substrate, and a second metal pad over the semiconductor substrate. In a case, the first metal pad is tape automated bonded thereto, and the second metal pad is solder bonded thereto. In another case, the first metal pad is tape automated bonded thereto, and the second metal pad is wirebonded thereto. In another case, the first metal pad is solder bonded thereto, and the second metal pad is wirebonded thereto. In another case, the first metal pad is bonded to an external circuitry using an anisotropic conductive film, and the second metal pad is solder bonded thereto. In another case, the first metal pad is bonded to an external circuitry using an anisotropic conductive film, and the second metal pad is wirebonded thereto.

摘要翻译： 芯片封装包括半导体衬底，半导体衬底上的第一金属焊盘和半导体衬底上的第二金属焊盘。 在这种情况下，第一金属焊盘是自动粘结到其上的，并且第二金属焊盘被焊接到其上。 在另一种情况下，第一金属垫是胶带自动粘合到其上，并且第二金属垫与其键合。 在另一种情况下，第一金属焊盘焊接到其上，并且第二金属焊盘与其键合。 在另一种情况下，使用各向异性导电膜将第一金属焊盘接合到外部电路，并且将第二金属焊盘焊接到其上。 在另一种情况下，使用各向异性导电膜将第一金属焊盘接合到外部电路，并且第二金属焊盘与其键合。