公开(公告)号：US08343828B2

公开(公告)日：2013-01-01

申请号：US13305072

申请日：2011-11-28

申请人： Gurtej Sandhu ,  Bhaskar Srinivasan

发明人： Gurtej Sandhu ,  Bhaskar Srinivasan

IPC分类号： H01L21/8234

CPC分类号： H01L21/04 ,  H01L27/1021 ,  H01L27/2418 ,  H01L29/1606 ,  H01L45/00

摘要： Some embodiments include methods of forming diodes. A stack may be formed over a first conductive material. The stack may include, in ascending order, a sacrificial material, at least one dielectric material, and a second conductive material. Spacers may be formed along opposing sidewalls of the stack, and then an entirety of the sacrificial material may be removed to leave a gap between the first conductive material and the at least one dielectric material. In some embodiments of forming diodes, a layer may be formed over a first conductive material, with the layer containing supports interspersed in sacrificial material. At least one dielectric material may be formed over the layer, and a second conductive material may be formed over the at least one dielectric material. An entirety of the sacrificial material may then be removed.

公开(公告)号：US20120326242A1

公开(公告)日：2012-12-27

申请号：US13605511

申请日：2012-09-06

申请人： Gurtej Sandhu ,  John K. Zahurak ,  Jay Parks

发明人： Gurtej Sandhu ,  John K. Zahurak ,  Jay Parks

IPC分类号： H01L27/088

CPC分类号： H01L27/2454 ,  H01L27/2463 ,  H01L29/7827 ,  H01L45/06 ,  H01L45/1233

摘要： A vertical semiconductor material mesa upstanding from a semiconductor base that forms a conductive channel between first and second doped regions. The first doped region is electrically coupled to one or more first silicide layers on the surface of the base. The second doped region is electrically coupled to one of a plurality of second silicide layers on the upper surface of the mesa. A gate conductor is provided on one or more sidewalls of the mesa.

公开(公告)号：US20120261638A1

公开(公告)日：2012-10-18

申请号：US13086321

申请日：2011-04-13

申请人： Scott E. Sills ,  Gurtej Sandhu

发明人： Scott E. Sills ,  Gurtej Sandhu

IPC分类号： H01L45/00

CPC分类号： H01L45/1226 ,  H01L27/2463 ,  H01L27/249 ,  H01L45/06 ,  H01L45/08 ,  H01L45/085 ,  H01L45/122 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147

摘要： This disclosure provides embodiments for the formation of vertical memory cell structures that may be implemented in RRAM devices. In one embodiment, memory cell area may be increased by varying word line height and/or word line interface surface characteristics to ensure the creation of a grain boundary that is suitable for formation of conductive pathways through an active layer of an RRAM memory cell. This may maintain continuum behavior while reducing random cell-to-cell variability that is often encountered at nanoscopic scales. In another embodiment, such vertical memory cell structures may be formed in multiple-tiers to define a three-dimensional RRAM memory array. Further embodiments also provide a spacer pitch-doubled RRAM memory array that integrates vertical memory cell structures.

摘要翻译： 本公开提供了可以在RRAM设备中实现的垂直存储器单元结构的形成的实施例。 在一个实施例中，可以通过改变字线高度和/或字线界面表面特性来增加存储器单元面积，以确保产生适于通过RRAM存储器单元的有源层形成导电路径的晶界。 这可以保持连续体行为，同时减少在纳米尺度上经常遇到的随机细胞间变异性。 在另一实施例中，这样的垂直存储单元结构可以以多层形成以定义三维RRAM存储器阵列。 另外的实施例还提供了一种集成垂直存储单元结构的间隔物间距加倍的RRAM存储器阵列。

公开(公告)号：US08274110B2

公开(公告)日：2012-09-25

申请号：US12469563

申请日：2009-05-20

申请人： Gurtej Sandhu ,  John K. Zahurak ,  Jay Parks

发明人： Gurtej Sandhu ,  John K. Zahurak ,  Jay Parks

IPC分类号： H01L29/66

CPC分类号： H01L27/2454 ,  H01L27/2463 ,  H01L29/7827 ,  H01L45/06 ,  H01L45/1233

摘要： A vertical semiconductor material mesa upstanding from a semiconductor base that forms a conductive channel between first and second doped regions. The first doped region is electrically coupled to one or more first silicide layers on the surface of the base. The second doped region is electrically coupled to one of a plurality of second silicide layers on the upper surface of the mesa. A gate conductor is provided on one or more sidewalls of the mesa.

摘要翻译： 从半导体基底直立的垂直半导体材料，其在第一和第二掺杂区域之间形成导电通道。 第一掺杂区域电耦合到基底表面上的一个或多个第一硅化物层。 第二掺杂区域电耦合到台面的上表面上的多个第二硅化物层中的一个。 栅极导体设置在台面的一个或多个侧壁上。

公开(公告)号：US08238151B2

公开(公告)日：2012-08-07

申请号：US12642533

申请日：2009-12-18

申请人： Jun Liu ,  Gurtej Sandhu

发明人： Jun Liu ,  Gurtej Sandhu

IPC分类号： G11C11/14

CPC分类号： G11C11/1675 ,  G11C11/161

摘要： A memory cell including magnetic materials and heating materials, and methods of programming the memory cell are provided. The memory cell includes a free region, a pinned region, and a heating region configured to generate and transfer heat to the free region when a programming current is directed to the cell. The heat transferred from the heating region increases the temperature of the free region, which decreases the magnetization and the critical switching current density of the free region. In some embodiments, the heating region may also provide a current path to the free region, and the magnetization of the free region may be switched according to the spin polarity of the programming current, programming the memory cell to a high resistance state or a low resistance state.

摘要翻译： 提供包括磁性材料和加热材料的存储单元，以及编程存储单元的方法。 存储单元包括自由区域，固定区域和加热区域，该区域被配置成当编程电流被引导到单元时，产生和传递热量到自由区域。 从加热区域传递的热量增加了自由区域的温度，这降低了自由区域的磁化强度和临界开关电流密度。 在一些实施例中，加热区域还可以提供到自由区域的电流路径，并且可以根据编程电流的自旋极性来切换自由区域的磁化，将存储器单元编程为高电阻状态或低电平状态 电阻状态。

公开(公告)号：US08216949B2

公开(公告)日：2012-07-10

申请号：US12707560

申请日：2010-02-17

申请人： Mirzafer K Abatchev ,  Gurtej Sandhu ,  Luan Tran ,  William T Rericha ,  D. Mark Durcan

发明人： Mirzafer K Abatchev ,  Gurtej Sandhu ,  Luan Tran ,  William T Rericha ,  D. Mark Durcan

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： H01L21/0337 ,  H01L21/0332 ,  H01L21/0338 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/32139 ,  Y10S438/947 ,  Y10S438/95

摘要： A method lor integrated circuit fabrication is disclosed. A spacer pattern is provided including a plurality ot spacers in an array region of a partially-fabricated integrated circuit. Each spacer is at least partly defined by opposing open volumes extending along lengths of the spacers. A pattern is subsequently defined in a periphery region of the partially-fabricated integrated circuit. A consolidated pattern is formed by concurrently transferring the spacer pattern and the pattern in the periphery region into an underlying masking layer. The consolidated pattern is transferred to an underlying substrate.

摘要翻译： 公开了一种用于集成电路制造的方法。 提供了一种间隔图案，其包括在部分制造的集成电路的阵列区域中的多个间隔物。 每个间隔物至少部分地通过沿间隔物的长度延伸的相对的开放体积限定。 随后在部分制造的集成电路的外围区域中限定图案。 通过将间隔物图案和外围区域中的图案同时转移到下面的掩模层中形成固结图案。 固结图案转移到下面的基底。

公开(公告)号：US08189450B2

公开(公告)日：2012-05-29

申请号：US12837984

申请日：2010-07-16

申请人： Jun Liu ,  Mike Violette ,  Gurtej Sandhu

发明人： Jun Liu ,  Mike Violette ,  Gurtej Sandhu

IPC分类号： B11B9/00

CPC分类号： G11B9/04

摘要： A data storage device and methods for storing and reading data are provided. The data storage device includes a data storage medium and second device. The data storage medium has an insulating layer, a first electrode layer over the insulating layer and at least one layer of resistance variable material over the first electrode layer. The second device includes a substrate and at least one conductive point configured to electrically contact the data storage medium.

摘要翻译： 提供了一种用于存储和读取数据的数据存储装置和方法。 数据存储装置包括数据存储介质和第二装置。 数据存储介质具有绝缘层，绝缘层上的第一电极层和第一电极层上的至少一层电阻可变材料。 第二装置包括基板和被配置为电接触数据存储介质的至少一个导电点。

公开(公告)号：US20120120721A1

公开(公告)日：2012-05-17

申请号：US13357527

申请日：2012-01-24

申请人： Jun Liu ,  Gurtej Sandhu

发明人： Jun Liu ,  Gurtej Sandhu

IPC分类号： G11C11/16 ,  H01L29/82

CPC分类号： G11C11/1675 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1695 ,  H01L43/02

摘要： Spin torque transfer magnetic random access memory devices configured to be programmed unidirectionally and methods of programming such devices. The devices include memory cells having two pinned layers and a free layer therebetween. By utilizing two pinned layers, the spin torque effect on the free layer from each of the two pinned layers, respectively, allows the memory cells to be programmed with unidirectional currents.

摘要翻译： 配置为单向编程的自旋扭矩传递磁性随机存取存储器件以及编程这种器件的方法。 这些装置包括具有两个钉扎层和其间的自由层的存储单元。 通过利用两个固定层，分别从两个固定层中的每一个自由层上的自旋转矩效应允许以单向电流编程存储器单元。

公开(公告)号：US08173550B2

公开(公告)日：2012-05-08

申请号：US13179851

申请日：2011-07-11

申请人： Sanket Sant ,  Gurtej Sandhu ,  Neal R. Rueger

发明人： Sanket Sant ,  Gurtej Sandhu ,  Neal R. Rueger

IPC分类号： H01L21/302

CPC分类号： H01L21/3088 ,  H01L21/0337 ,  H01L21/3085 ,  H01L21/3086 ,  H01L21/76802 ,  H01L27/1052

摘要： Multiple pitch-multiplied spacers are used to form mask patterns having features with exceptionally small critical dimensions. One of each pair of spacers formed around a plurality of mandrels is removed and alternating layers, formed of two mutually selectively etchable materials, are deposited around the remaining spacers. Layers formed of one of the materials are then etched, leaving behind vertically-extending layers formed of the other of the materials, which form a mask pattern. Alternatively, instead of depositing alternating layers, amorphous carbon is deposited around the remaining spacers followed by a plurality of cycles of forming pairs of spacers on the amorphous carbon, removing one of the pairs of spacers and depositing an amorphous carbon layer. The cycles can be repeated to form the desired pattern. Because the critical dimensions of some features in the pattern can be set by controlling the width of the spaces between spacers, exceptionally small mask features can be formed.

摘要翻译： 使用多个间距倍数的间隔物来形成具有特别小的临界尺寸的特征的掩模图案。 去除围绕多个心轴形成的每对间隔件中的一个，并且由两个相互选择性可蚀刻的材料形成的交替层围绕剩余的间隔物沉积。 然后蚀刻由一种材料形成的层，留下由形成掩模图案的另一种材料形成的垂直延伸层。 或者，代替沉积交替的层，非晶碳沉积在剩余的间隔物周围，随后在无定形碳上形成成对隔离物的多个循环，去除一对隔离物之一并沉积无定形碳层。 可以重复循环以形成所需的图案。 由于图案中的某些特征的临界尺寸可以通过控制间隔物之间​​的间隔的宽度来设定，所以可以形成特别小的掩模特征。

公开(公告)号：US08034655B2

公开(公告)日：2011-10-11

申请号：US12099267

申请日：2008-04-08

申请人： John Smythe ,  Bhaskar Srinivasan ,  Gurtej Sandhu

发明人： John Smythe ,  Bhaskar Srinivasan ,  Gurtej Sandhu

IPC分类号： H01L21/8239

CPC分类号： H01L45/04 ,  G11C11/56 ,  G11C13/00 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1666

摘要： A method of forming a non-volatile resistive oxide memory cell includes forming a first conductive electrode of the memory cell as part of a substrate. Insulative material is deposited over the first electrode. An opening is formed into the insulative material over the first electrode. The opening includes sidewalls and a base. The opening sidewalls and base are lined with a multi-resistive state layer comprising multi-resistive state metal oxide-comprising material which less than fills the opening. A second conductive electrode of the memory cell is formed within the opening laterally inward of the multi-resistive state layer lining the sidewalls and elevationally over the multi-resistive state layer lining the base. Other aspects and implementations are contemplated.

摘要翻译： 形成非易失性电阻氧化物存储单元的方法包括：形成存储单元的第一导电电极作为衬底的一部分。 绝缘材料沉积在第一电极上。 在第一电极上形成绝缘材料的开口。 开口包括侧壁和底座。 开口侧壁和基底衬有包含少于填充开口的多电阻态金属氧化物材料的多电阻状态层。 存储单元的第二导电电极形成在多个电阻状态层的横向内侧的开口的内部，该电阻层衬在侧壁上，并且在衬底基底上的多电阻状态层的顶部形成。 考虑了其他方面和实现。