公开(公告)号：US06982468B2

公开(公告)日：2006-01-03

申请号：US10942014

申请日：2004-09-16

申请人： Shimpei Tsujikawa ,  Toshiyuki Mine ,  Jiro Yugami ,  Natsuki Yokoyama ,  Tsuyoshi Yamauchi

发明人： Shimpei Tsujikawa ,  Toshiyuki Mine ,  Jiro Yugami ,  Natsuki Yokoyama ,  Tsuyoshi Yamauchi

IPC分类号： H01L29/76

CPC分类号： H01L21/823857 ,  H01L21/823462

摘要： A semiconductor device and a method for manufacturing the same of forming a silicon nitride film selectively without giving damages or contaminations to a surface of the silicon substrate thereby forming different types of gate dielectrics in one identical silicon substrate, are obtained by forming a silicon dioxide on the surface of a silicon substrate, then removing a portion thereof, forming a silicon nitride film to the surface of the substrate from which the silicon dioxide has been removed and, simultaneously, introducing nitrogen to the surface of the silicon dioxide which is left not being removed or, alternatively, depositing a silicon dioxide on the surface of the silicon substrate by chemical vapor deposition, then removing a portion thereof, forming a silicon nitride film on the surface of a substrate from which the silicon dioxide has been removed, and, simultaneously, introducing nitrogen to the surface of the silicon dioxide left not being removed, successively, dissolving and removing nitrogen-introduced silicon oxide film to expose the surface of the substrate and oxidizing the exposed surface of the silicon substrate and the silicon nitride film

摘要翻译： 一种半导体器件及其制造方法，其选择性地形成氮化硅膜，而不会对硅衬底的表面造成损害或污染，从而在一个相同的硅衬底中形成不同类型的栅极电介质，通过在二氧化硅上形成二氧化硅 硅衬底的表面，然后去除其一部分，在已经除去二氧化硅的衬底的表面上形成氮化硅膜，同时将氮引入二氧化硅的不是 去除或者通过化学气相沉积在硅衬底的表面上沉积二氧化硅，然后去除其一部分，在去除二氧化硅的衬底的表面上形成氮化硅膜，同时 将氮气引入未被除去的二氧化硅的表面，依次溶解 并且去除引入氮的氧化硅膜以暴露衬底的表面并氧化硅衬底和氮化硅膜的暴露表面

公开(公告)号：US06521943B1

公开(公告)日：2003-02-18

申请号：US09520346

申请日：2000-03-07

申请人： Toshiyuki Mine ,  Jiro Yugami ,  Takashi Kobayashi ,  Masahiro Ushiyama

发明人： Toshiyuki Mine ,  Jiro Yugami ,  Takashi Kobayashi ,  Masahiro Ushiyama

IPC分类号： H01L29788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7883

摘要： Disclosed is a semiconductor device (e.g., nonvolatile semiconductor memory device) and method of forming the device. The device includes a gate electrode (e.g., floating gate electrode) having a first layer of an amorphous silicon film, or a polycrystalline silicon thin film or a film of a combination of amorphous and polycrystalline silicon, on the gate insulating film. Where the film includes polycrystalline silicon, the thickness of the film is less than 10 nm. A thicker polycrystalline silicon film can be provided on or overlying the first layer. The memory device can increase the write/erase current significantly without increasing the low electric field leakage current after application of stresses, which in turn reduces write/erase time substantially. In forming the semiconductor device, a thin amorphous or polycrystalline silicon film can be provided on the gate insulating film, and a thin insulating film provided on the amorphous silicon film, with a thicker polycrystalline silicon film provided on or overlying the thin insulating film. Where the thin silicon film is amorphous silicon, it can then be polycrystallized, although it need not be. Also disclosed is a technique for selective crystallization of amorphous silicon layers, based upon layer thickness.

摘要翻译： 公开了一种半导体器件（例如非易失性半导体存储器件）及其形成方法。 该器件包括在栅极绝缘膜上具有非晶硅膜的第一层或多晶硅薄膜或非晶硅和多晶硅的组合的膜的栅电极（例如，浮栅电极）。 当膜包括多晶硅时，膜的厚度小于10nm。 可以在第一层上或覆盖第一层上提供较厚的多晶硅膜。 存储器件可以显着增加写入/擦除电流，而不会在施加应力之后增加低电场漏电流，这反过来大大降低了写入/擦除时间。 在形成半导体器件时，可以在栅极绝缘膜上提供薄的非晶或多晶硅膜，以及设置在非晶硅膜上的薄绝缘膜，其上设置有较厚的多晶硅膜或覆盖薄绝缘膜。 在薄硅膜是非晶硅的情况下，其然后可以多晶化，尽管不需要。 还公开了基于层厚度的非晶硅层的选择性结晶的技术。

公开(公告)号：US6144062A

公开(公告)日：2000-11-07

申请号：US41793

申请日：1998-03-13

申请人： Toshiyuki Mine ,  Jiro Yugami ,  Takashi Kobayashi ,  Masahiro Ushiyama

发明人： Toshiyuki Mine ,  Jiro Yugami ,  Takashi Kobayashi ,  Masahiro Ushiyama

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7883

摘要： Disclosed is a semiconductor device (e.g., nonvolatile semiconductor memory device) and method of forming the device. The device includes a gate electrode (e.g., floating gate electrode) having a first layer of an amorphous silicon film, or a polycrystalline silicon thin film or a film of a combination of amorphous and polycrystalline silicon, on the gate insulating film. Where the film includes polycrystalline silicon, the thickness of the film is less than 10 nm. A thicker polycrystalline silicon film can be provided on or overlying the first layer. The memory device can increase the write/erase current significantly without increasing the low electric field leakage current after application of stresses, which in turn reduces write/erase time substantially. In forming the semiconductor device, a thin amorphous or polycrystalline silicon film can be provided on the gate insulating film, and a thin insulating film provided on the amorphous silicon film, with a thicker polycrystalline silicon film provided on or overlying the thin insulating film. Where the thin silicon film is amorphous silicon, it can then be polycrystallized, although it need not be. Also disclosed is a technique for selective crystallization of amorphous silicon layers, based upon layer thickness.

公开(公告)号：US5091761A

公开(公告)日：1992-02-25

申请号：US384821

申请日：1989-07-25

申请人： Atsushi Hiraiwa ,  Shinichiro Kimura ,  Toshiyuki Mine ,  Takashi Kobayashi ,  Tokuo Kure ,  Shinpei Iijima ,  Jiro Yugami

发明人： Atsushi Hiraiwa ,  Shinichiro Kimura ,  Toshiyuki Mine ,  Takashi Kobayashi ,  Tokuo Kure ,  Shinpei Iijima ,  Jiro Yugami

IPC分类号： H01L27/108

CPC分类号： H01L27/10808

摘要： Disclosed is a semiconductor device including a charge storage capacitor having a storage electrode which is electrically connected to a switching transistor through a contact hole provided in an insulator and which has a greater film thickness than the radius of the contact hole, at least a part of the storage electrode being disposed above a data line. It is possible to reduce the memory cell area while preventing lowering in the capacitance, and thus realize high density and high integration of semiconductor devices.

摘要翻译： 公开了一种半导体器件，包括具有存储电极的电荷存储电容器，该存储电极通过设置在绝缘体中的接触孔与开关晶体管电连接并且具有比接触孔的半径更大的膜厚度，至少部分 所述存储电极设置在数据线的上方。 可以在防止电容降低的同时减小存储单元面积，从而实现半导体器件的高密度和高集成度。

公开(公告)号：US08664053B2

公开(公告)日：2014-03-04

申请号：US13165821

申请日：2011-06-22

申请人： Jiro Yugami

发明人： Jiro Yugami

IPC分类号： H01L29/772 ,  H01L21/28

CPC分类号： H01L29/0653 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/76224 ,  H01L21/823481 ,  H01L29/49 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/78

摘要： A device isolation region is made of a silicon oxide film embedded in a trench, an upper portion thereof is protruded from a semiconductor substrate, and a sidewall insulating film made of silicon nitride or silicon oxynitride is formed on a sidewall of a portion of the device isolation region which is protruded from the semiconductor substrate. A gate insulating film of a MISFET is made of an Hf-containing insulating film containing hafnium, oxygen and an element for threshold reduction as main components, and a gate electrode that is a metal gate electrode extends on an active region, the sidewall insulating film and the device isolation region. The element for threshold reduction is a rare earth or Mg when the MISFET is an n-channel MISFET, and the element for threshold reduction is Al, Ti or Ta when the MISFET is a p-channel MISFET.

摘要翻译： 器件隔离区域由嵌入在沟槽中的氧化硅膜制成，其上部从半导体衬底突出，并且在器件的一部分的侧壁上形成由氮化硅或氮氧化硅制成的侧壁绝缘膜 隔离区域从半导体衬底突出。 MISFET的栅极绝缘膜由含有铪，氧和用于阈值还原的元素作为主要成分的含Hf绝缘膜制成，作为金属栅电极的栅电极在有源区上延伸，侧壁绝缘膜 和器件隔离区。 当MISFET为p沟道MISFET时，MISFET为n沟道MISFET时，用于阈值降低的元件为稀土或Mg，阈值降低元件为Al，Ti或Ta。

公开(公告)号：US20120248545A1

公开(公告)日：2012-10-04

申请号：US13515500

申请日：2009-12-24

申请人： Jiro Yugami

发明人： Jiro Yugami

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823857 ,  H01L21/28194 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A p-type MIS transistor Qp arranged in a pMIS region Rp of a silicon substrate 1 includes a pMIS gate electrode GEp formed so as to interpose a pMIS gate insulating film GIp formed of a first insulating film z1 and a first high-dielectric film hk1, and an n-type MIS transistor Qn arranged in an nMIS region Rn includes an nMIS gate electrode GEn formed so as to interpose an nMIS gate insulating film GIn formed of a first insulating film z1 and a second high-dielectric film hk2. The first high-dielectric film hk1 is formed of an insulating film mainly made of hafnium and oxygen with containing aluminum, titanium, or tantalum. Also, the second high-dielectric film hk2 is formed of an insulating film mainly made of hafnium, silicon, and oxygen with containing an element of any of group Ia, group IIa, and group IIIa.

摘要翻译： 布置在硅衬底1的pMIS区域Rp中的p型MIS晶体管Qp包括pMIS栅极电极GEp，其形成为将由第一绝缘膜z1和第一高介电膜hk1形成的pMIS栅极绝缘膜GIp ，并且配置在nMIS区域Rn中的n型MIS晶体管Qn包括形成为以由第一绝缘膜z1和第二高介电膜hk2形成的nMIS栅极绝缘膜GIn形成的nMIS栅电极GEn。 第一高电介质膜hk1由主要由铪和含有铝，钛或钽的氧构成的绝缘膜形成。 此外，第二高电介质膜hk2由主要由铪，硅和氧制成的绝缘膜形成，其含有Ia，IIa和IIIa族中任一种的元素。

公开(公告)号：US06897104B2

公开(公告)日：2005-05-24

申请号：US10452126

申请日：2003-06-03

申请人： Shimpei Tsujikawa ,  Toshiyuki Mine ,  Jiro Yugami ,  Natsuki Yokoyama ,  Tsuyoshi Yamauchi

发明人： Shimpei Tsujikawa ,  Toshiyuki Mine ,  Jiro Yugami ,  Natsuki Yokoyama ,  Tsuyoshi Yamauchi

IPC分类号： H01L21/316 ,  H01L21/318 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/8238

CPC分类号： H01L21/823857 ,  H01L21/823462

摘要： A semiconductor device and a method for manufacturing the same of forming a silicon nitride film selectively without giving damages or contaminations to a surface of the silicon substrate thereby forming different types of gate dielectrics in one identical silicon substrate, are obtained by forming a silicon dioxide on the surface of a silicon substrate, then removing a portion thereof, forming a silicon nitride film to the surface of the substrate from which the silicon dioxide has been removed and, simultaneously, introducing nitrogen to the surface of the silicon dioxide which is left not being removed or, alternatively, depositing a silicon dioxide on the surface of the silicon substrate by chemical vapor deposition, then removing a portion thereof, forming a silicon nitride film on the surface of a substrate from which the silicon dioxide has been removed, and, simultaneously, introducing nitrogen to the surface of the silicon dioxide left not being removed, successively, dissolving and removing nitrogen-introduced silicon oxide film to expose the surface of the substrate and oxidizing the exposed surface of the silicon substrate and the silicon nitride film.

摘要翻译： 一种半导体器件及其制造方法，其选择性地形成氮化硅膜，而不会对硅衬底的表面造成损害或污染，从而在一个相同的硅衬底中形成不同类型的栅极电介质，通过在二氧化硅上形成二氧化硅 硅衬底的表面，然后去除其一部分，在已经除去二氧化硅的衬底的表面上形成氮化硅膜，同时将氮引入二氧化硅的不是 去除或者通过化学气相沉积在硅衬底的表面上沉积二氧化硅，然后去除其一部分，在去除二氧化硅的衬底的表面上形成氮化硅膜，同时 将氮气引入未被除去的二氧化硅的表面，依次溶解 并且移除氮导入的氧化硅膜以暴露衬底的表面并氧化硅衬底和氮化硅膜的暴露表面。

公开(公告)号：US20050104141A1

公开(公告)日：2005-05-19

申请号：US11000992

申请日：2004-12-02

申请人： Jiro Yugami ,  Natsuki Yokoyama ,  Toshiyuki Mine ,  Yasushi Goto

发明人： Jiro Yugami ,  Natsuki Yokoyama ,  Toshiyuki Mine ,  Yasushi Goto

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/49 ,  H01L29/51 ,  H01L21/336 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L21/28194 ,  H01L21/28079 ,  H01L21/28114 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823456 ,  H01L21/823462 ,  H01L29/42368 ,  H01L29/495 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

摘要： There is provided a semiconductor device configured as follows. On a semiconductor substrate, a titanium oxide film which is an insulating film having a higher dielectric constant than that of a silicon dioxide film is formed as a gate insulating film, and a gate electrode is disposed thereon, resulting in a field effect transistor. The end portions in the gate length direction of the titanium oxide film are positioned inwardly from the respective end portions on the source side and on the drain side of the gate electrode, and the end portions of the titanium oxide film are positioned in a region in which the gate electrode overlaps with the source region and the drain region in plan configuration. This semiconductor device operates at a high speed, and is excellent in short channel characteristics and driving current. Further, in the semiconductor device, the amount of metallic elements introduced into a silicon substrate is small.

摘要翻译： 提供如下配置的半导体器件。 在半导体衬底上形成作为绝缘膜的介电常数高于二氧化硅膜的氧化钛膜作为栅极绝缘膜，并且在其上设置栅电极，得到场效应晶体管。 氧化钛膜的栅极长度方向的端部位于栅电极的源极侧和漏极侧的各端部的内侧，氧化钛膜的端部位于 其中栅电极以平面构型与源区和漏区重叠。 该半导体器件以高速度工作，并且具有优异的短沟道特性和驱动电流。 此外，在半导体器件中，导入硅衬底的金属元素的量小。

公开(公告)号：US20050029600A1

公开(公告)日：2005-02-10

申请号：US10942014

申请日：2004-09-16

申请人： Shimpei Tsujikawa ,  Toshiyuki Mine ,  Jiro Yugami ,  Natsuki Yokoyama ,  Tsuyoshi Yamauchi

发明人： Shimpei Tsujikawa ,  Toshiyuki Mine ,  Jiro Yugami ,  Natsuki Yokoyama ,  Tsuyoshi Yamauchi

IPC分类号： H01L21/316 ,  H01L21/318 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/44 ,  H01L21/8238 ,  H01L29/76 ,  H01L31/062 ,  H01L31/119

CPC分类号： H01L21/823857 ,  H01L21/823462

摘要： A semiconductor device and a method for manufacturing the same of forming a silicon nitride film selectively without giving damages or contaminations to a surface of the silicon substrate thereby forming different types of gate dielectrics in one identical silicon substrate, are obtained by forming a silicon dioxide on the surface of a silicon substrate, then removing a portion thereof, forming a silicon nitride film to the surface of the substrate from which the silicon dioxide has been removed and, simultaneously, introducing nitrogen to the surface of the silicon dioxide which is left not being removed or, alternatively, depositing a silicon dioxide on the surface of the silicon substrate by chemical vapor deposition, then removing a portion thereof, forming a silicon nitride film on the surface of a substrate from which the silicon dioxide has been removed, and, simultaneously, introducing nitrogen to the surface of the silicon dioxide left not being removed, successively, dissolving and removing nitrogen-introduced silicon oxide film to expose the surface of the substrate and oxidizing the exposed surface of the silicon substrate and the silicon nitride film

摘要翻译： 一种半导体器件及其制造方法，其选择性地形成氮化硅膜，而不会对硅衬底的表面造成损害或污染，从而在一个相同的硅衬底中形成不同类型的栅极电介质，通过在二氧化硅上形成二氧化硅 硅衬底的表面，然后去除其一部分，在已经除去二氧化硅的衬底的表面上形成氮化硅膜，同时将氮引入二氧化硅的不是 去除或者通过化学气相沉积在硅衬底的表面上沉积二氧化硅，然后去除其一部分，在去除二氧化硅的衬底的表面上形成氮化硅膜，同时 将氮气引入未被除去的二氧化硅的表面，依次溶解 并且去除引入氮的氧化硅膜以暴露衬底的表面并氧化硅衬底和氮化硅膜的暴露表面

公开(公告)号：US06723625B2

公开(公告)日：2004-04-20

申请号：US10251753

申请日：2002-09-23

申请人： Toshiyuki Mine ,  Jiro Yugami ,  Takashi Kobayashi ,  Masahiro Ushiyama

发明人： Toshiyuki Mine ,  Jiro Yugami ,  Takashi Kobayashi ,  Masahiro Ushiyama

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/7883

摘要： Disclosed is a semiconductor device (e.g., nonvolatile semiconductor memory device) and method of forming the device. The device includes a gate electrode (e.g., floating gate electrode) having a first layer of an amorphous silicon film, or a polycrystalline silicon thin film or a film of a combination of amorphous and polycrystalline silicon, on the gate insulating film. Where the film includes polycrystalline silicon, the thickness of the film is less than 10 nm. A thicker polycrystalline silicon film can be provided on or overlying the first layer. The memory device can increase the write/erase current significantly without increasing the low electric field leakage current after application of stresses, which in turn reduces write/erase time substantially. In forming the semiconductor device, a thin amorphous or polycrystalline silicon film can be provided on the gate insulating film, and a thin insulating film provided on the amorphous silicon film, with a thicker polycrystalline silicon film provided on or overlying the thin insulating film. Where the thin silicon film is amorphous silicon, it can then be polycrystallized, although it need not be. Also disclosed is a technique for selective crystallization of amorphous silicon layers, based upon layer thickness.

摘要翻译： 公开了一种半导体器件（例如非易失性半导体存储器件）及其形成方法。 该器件包括在栅极绝缘膜上具有非晶硅膜的第一层或多晶硅薄膜或非晶硅和多晶硅的组合的膜的栅电极（例如，浮栅电极）。 当膜包括多晶硅时，膜的厚度小于10nm。 可以在第一层上或覆盖第一层上提供较厚的多晶硅膜。 存储器件可以显着增加写入/擦除电流，而不会在施加应力之后增加低电场漏电流，这反过来大大降低了写入/擦除时间。 在形成半导体器件时，可以在栅极绝缘膜上提供薄的非晶或多晶硅膜，以及设置在非晶硅膜上的薄绝缘膜，其上设置有较厚的多晶硅膜或覆盖薄绝缘膜。 在薄硅膜是非晶硅的情况下，其然后可以多晶化，尽管不需要。 还公开了基于层厚度的非晶硅层的选择性结晶的技术。