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    High speed semiconductor memory device with short word line switching time
    11.
    发明授权
    High speed semiconductor memory device with short word line switching time 有权
    具有短字线切换时间的高速半导体存储器件

    公开(公告)号：US06366507B1

    公开(公告)日：2002-04-02

    申请号：US09653900

    申请日：2000-09-01

    申请人： Takashi Akioka ,  Masao Shinozaki

    发明人： Takashi Akioka ,  Masao Shinozaki

    IPC分类号： G11C700

    CPC分类号： G11C7/22 ,  G11C7/1072 ,  G11C8/08 ,  G11C11/413 ,  G11C2207/2281

    摘要： Setting means (such as fuse circuits) for adjusting the timings of various signals such as an activation timing of a sense amplifier, a fall timing of a word line, a recovery operation (equalization) of a bit lines and so forth, checking an operation in a test stage of a chip, and permanently programming (fixing) the timing of an internal signal to the condition of the highest operation speed that can be confirmed as acquirable in this check stage, is provided.

    摘要翻译： 用于调整诸如读出放大器的激活定时，字线的下降定时，位线的恢复操作（均衡）等各种信号的定时的设置装置（例如熔丝电路），检查操作 在芯片的测试阶段，并且将内部信号的定时永久地编程（固定）到在该检查阶段可以被确认为可获取的最高操作速度的条件。

    Semiconductor memory device
    17.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US07903490B2

    公开(公告)日：2011-03-08

    申请号：US12232369

    申请日：2008-09-16

    申请人： Hajime Sato ,  Masao Shinozaki

    发明人： Hajime Sato ,  Masao Shinozaki

    IPC分类号： G11C7/02

    CPC分类号： G11C7/18 ,  G11C7/02 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069 ,  G11C7/1078 ,  G11C7/1084 ,  G11C11/4087 ,  G11C11/4093 ,  G11C11/4097

    摘要： The present invention provides a semiconductor memory device in which the number of write amplifiers is decreased by increasing the number of bit line pairs connected to one pair of common write data lines. Further, by decreasing the number of bit line pairs connected to one pair of common read data lines, parasitic capacitance connected to the pair of common read data lines is reduced and, accordingly, time in which the potential difference between the pair of common read data lines increases is shortened. Thus, while preventing enlargement of the chip layout area, read time can be shortened.

    摘要翻译： 本发明提供一种半导体存储器件，其中通过增加连接到一对公共写入数据线的位线对的数量来减少写入放大器的数量。 此外，通过减少连接到一对公共读取数据线的位线对的数量，减少连接到该对公共读取数据线的寄生电容，并且因此减小了该对公共读取数据之间的电位差 线条增加缩短。 因此，在防止芯片布局区域扩大的同时，可以缩短读取时间。

    Semiconductor integrated circuit device
    18.
    发明申请
    Semiconductor integrated circuit device 审中-公开

    公开(公告)号：US20080279033A1

    公开(公告)日：2008-11-13

    申请号：US12219050

    申请日：2008-07-15

    申请人： Masao Shinozaki ,  Daisuke Shimadu

    发明人： Masao Shinozaki ,  Daisuke Shimadu

    IPC分类号： G11C8/08

    CPC分类号： G11C8/08 ,  G11C8/14

    摘要： A semiconductor integrated circuit device provided with a memory circuit having a word line selection circuit with reduced leakage current is provided. The memory circuit includes: second word lines with which memory cells are connected; multiple bit lines that are extended in a direction orthogonal thereto and electrically connected with memory cells corresponding to selected second word lines of a plurality of the second word lines; and word drivers, constructed of CMOS inverter circuits, that select or deselect the second word lines. The sources of p-channel MOSFETs that constitute a plurality of word drivers including second word lines corresponding to selected bit lines are supplied with a voltage at a level at which second word lines are selected. The sources of the p-channel MOSFETs of the other word drivers are supplied with a voltage corresponding to a level at which second word lines are deselected.

    Semiconductor integrated circuit
    19.
    发明授权
    Semiconductor integrated circuit 有权
    半导体集成电路

    公开(公告)号：US07296173B2

    公开(公告)日：2007-11-13

    申请号：US10768441

    申请日：2004-02-02

    申请人： Hiroaki Nambu ,  Masao Shinozaki ,  Kazuo Kanetani ,  Hideto Kazama

    发明人： Hiroaki Nambu ,  Masao Shinozaki ,  Kazuo Kanetani ,  Hideto Kazama

    IPC分类号： G06F1/12 ,  G06F13/42 ,  H04L5/00 ,  H04L7/00

    CPC分类号： G11C11/413 ,  G06F1/04 ,  G11C11/419

    摘要： A semiconductor integrated circuit is provided in which the timing margin for fetching data is prevented from being reduced even in the case where the duty ratio of a clock signal is different from 50%. The semiconductor integrated circuit includes: a clock input terminal for receiving a clock signal; a data input terminal for receiving a data signal; internal clock generating circuits for generating an internal clock signal which is switched at an intermediate timing between the i-th (i: an integer of 1 or larger) switch timing and the (i+1)th switch timing of the clock signal; and a latch circuit for latching the data signal synchronously with the internal clock signal. An internal clock signal which is switched at an intermediate timing between the i-th switch timing and the (i+1)th switch timing of the clock signal is generated, and the data signal is fetched synchronously with the internal clock signal.

    摘要翻译： 提供一种半导体集成电路，其中即使在时钟信号的占空比不同于50％的情况下，也可以防止用于取出数据的定时裕度。 半导体集成电路包括：时钟输入端子，用于接收时钟信号; 用于接收数据信号的数据输入端; 内部时钟发生电路，用于产生在第i（i：1或更大的整数）切换定时与时钟信号的第（i + 1）切换定时之间的中间定时切换的内部时钟信号; 以及与内部时钟信号同步地锁存数据信号的锁存电路。 产生在时钟信号的第i开关定时和第（i + 1）开关定时之间的中间定时切换的内部时钟信号，并且与内部时钟信号同步取出数据信号。

    Semiconductor device
    20.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08611166B2

    公开(公告)日：2013-12-17

    申请号：US13584271

    申请日：2012-08-13

    申请人： Masao Shinozaki

    发明人： Masao Shinozaki

    IPC分类号： G11C7/02

    CPC分类号： G11C11/413

    摘要： There is provided a technique for ensuring both an SNM and a write margin simultaneously in a semiconductor device having static memory cells. A semiconductor device has a plurality of static memory cells. The semiconductor device includes a memory cell array having the static memory cells arranged in a matrix, a temperature sensor circuit for sensing a temperature in the semiconductor device, and a word driver for controlling a voltage supplied to a word line of the memory cell array based on an output of the temperature sensor circuit at the time of writing to or reading from a memory cell.

    摘要翻译： 提供了一种用于在具有静态存储单元的半导体器件中同时确保SNM和写入裕度的技术。 半导体器件具有多个静态存储单元。 半导体器件包括具有以矩阵形式布置的静态存储单元的存储单元阵列，用于感测半导体器件中的温度的温度传感器电路和用于控制提供给存储单元阵列的字线的电压的字驱动器 在写入或从存储单元读取时在温度传感器电路的输出上。