公开(公告)号：US20080290403A1

公开(公告)日：2008-11-27

申请号：US12123072

申请日：2008-05-19

申请人： Syotaro ONO ,  Wataru Saito ,  Masakatsu Takashita ,  Yasuto Sumi ,  Masaru Izumisawa ,  Hiroshi Ohta ,  Wataru Sekine

发明人： Syotaro ONO ,  Wataru Saito ,  Masakatsu Takashita ,  Yasuto Sumi ,  Masaru Izumisawa ,  Hiroshi Ohta ,  Wataru Sekine

IPC分类号： H01L29/78

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0878 ,  H01L29/7395 ,  H01L29/861 ,  H01L29/868 ,  H01L29/872

摘要： A semiconductor apparatus includes a first semiconductor layer, a second semiconductor layer provided on a major surface of the first semiconductor layer, a third semiconductor layer provided on the major surface and being adjacent to the second semiconductor layer, a termination semiconductor layer provided on the major surface of the first semiconductor layer in a termination region outside the device region, a channel stop layer, and a channel stop electrode. The channel stop layer is provided in contact with the termination semiconductor layer on the major surface of the first semiconductor layer in an outermost peripheral portion outside the termination semiconductor layer and has a higher impurity concentration than the termination semiconductor layer. The channel stop electrode is provided on at least part of a surface of the channel stop layer and projects toward the termination semiconductor layer beyond at least a superficial portion of the channel stop layer.

摘要翻译： 半导体装置包括第一半导体层，设置在第一半导体层的主表面上的第二半导体层，设置在主表面上并与第二半导体层相邻的第三半导体层，设置在主体上的端接半导体层 在器件区域外的终端区域中的第一半导体层的表面，沟道阻挡层和沟道停止电极。 沟道阻挡层设置成与终端半导体层外部的最外周部分中的第一半导体层的主表面上的端接半导体层接触，并且具有比端接半导体层更高的杂质浓度。 通道阻挡电极设置在通道阻挡层的表面的至少一部分上，并且朝向端子半导体层突出超过通道阻挡层的至少表面部分。

公开(公告)号：US20100096692A1

公开(公告)日：2010-04-22

申请号：US12537219

申请日：2009-08-06

申请人： Wataru SAITO ,  Syotaro ONO ,  Nana HATANO ,  Hiroshi OHTA ,  Miho WATANABE

发明人： Wataru SAITO ,  Syotaro ONO ,  Nana HATANO ,  Hiroshi OHTA ,  Miho WATANABE

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/7806

摘要： A semiconductor device of the invention includes: a super junction structure of an n-type pillar layer and a p-type pillar layer; a base layer provided on the p-type pillar layer; a source layer selectively provided on a surface of the base layer; a gate insulating film provided on a portion being in contact with the base layer, a portion being in contact with the source layer and a portion being in contact with the n-type pillar layer on a portion of a junction between the n-type pillar layer and the p-type pillar layer; a control electrode provided opposed to the base layer, the source layer and the n-type pillar layer through the gate insulating film; and a source electrode electrically connected to the base layer, the source layer and the n-type layer. The source electrode is contact with the surface of the n-type pillar layer located between the control electrodes to form a Schottky junction.

摘要翻译： 本发明的半导体器件包括：n型柱层和p型柱层的超结结构; 设置在p型支柱层上的基底层; 源层选择性地设置在基层的表面上; 设置在与所述基底层接触的部分上的栅极绝缘膜，与所述源极层接触的部分和在所述n型支柱的接合部的一部分上与所述n型支柱层接触的部分 层和p型支柱层; 控制电极，其通过所述栅极绝缘膜与所述基极层，所述源极层和所述n型支柱层相对设置; 以及与基极层，源极层和n型层电连接的源电极。 源电极与位于控制电极之间的n型支柱层的表面接触以形成肖特基结。

公开(公告)号：US20120074491A1

公开(公告)日：2012-03-29

申请号：US13234802

申请日：2011-09-16

申请人： Hiroshi OHTA ,  Yasuto SUMI ,  Kiyoshi KIMURA ,  Junji SUZUKI ,  Hiroyuki IRIFUNE ,  Wataru SAITO ,  Syotaro ONO

发明人： Hiroshi OHTA ,  Yasuto SUMI ,  Kiyoshi KIMURA ,  Junji SUZUKI ,  Hiroyuki IRIFUNE ,  Wataru SAITO ,  Syotaro ONO

IPC分类号： H01L27/088

CPC分类号： H01L29/78 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/42356 ,  H01L29/42372 ,  H01L29/7811 ,  H01L29/7813

摘要： In general, according to one embodiment, a power semiconductor device includes a first pillar region, a second pillar region, and an epitaxial layer of a first conductivity type on a first semiconductor layer. The first pillar region is composed of a plurality of first pillar layers of a second conductivity type and a plurality of second pillar layers of the first conductivity type alternately arranged along a first direction. The second pillar region is adjacent to the first pillar region along the first direction and includes a third pillar layer of the second conductivity type, a fourth pillar layer of the first conductivity type, and a fifth pillar layer of the second conductivity type in this order along the first direction. A plurality of second base layers of the second conductivity type electrically connected, respectively, onto the third pillar layer and the fifth pillar layer and spaced from each other.

摘要翻译： 通常，根据一个实施例，功率半导体器件包括在第一半导体层上的第一导电类型的第一柱状区域，第二柱状区域和外延层。 第一支柱区域由第一导电类型的多个第一支柱层和沿第一方向交替布置的第一导电类型的多个第二支柱层组成。 第二柱状区域沿着第一方向与第一柱状区域相邻，并且具有第二导电型的第三柱状层，第一导电型的第四柱状层和第二导电型的第五柱状层 沿着第一个方向。 多个第二导电类型的第二基极层分别电连接到第三柱层和第五柱层上并彼此间隔开。

公开(公告)号：US20110227154A1

公开(公告)日：2011-09-22

申请号：US13052032

申请日：2011-03-18

申请人： Syotaro ONO ,  Wataru Saito ,  Munehisa Yabuzaki ,  Shunji Taniuchi ,  Miho Watanabe

发明人： Syotaro ONO ,  Wataru Saito ,  Munehisa Yabuzaki ,  Shunji Taniuchi ,  Miho Watanabe

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66712

摘要： A semiconductor device comprising: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type formed on the first semiconductor layer; a first buried layer of the first conductivity type selectively formed in the second semiconductor layer and having a first peak impurity concentration at a first depth; a second buried layer of a second conductivity type selectively formed in the second semiconductor layer and having a second peak impurity concentration at a second depth; a base layer of the second conductivity type selectively formed in the second semiconductor layer and overlapping with an upper portion of the second buried layer; a source layer of the first conductivity type selectively formed in the base layer; and a gate electrode formed on the base layer and on the second semiconductor layer above the first buried layer with a gate insulating film being interposed therebetween.

摘要翻译： 一种半导体器件，包括：第一导电类型的第一半导体层; 形成在第一半导体层上的第一导电类型的第二半导体层; 第一导电类型的第一掩埋层选择性地形成在第二半导体层中，并且在第一深度处具有第一峰值杂质浓度; 第二导电类型的第二掩埋层选择性地形成在第二半导体层中，并且在第二深度具有第二峰值杂质浓度; 第二导电类型的基极层选择性地形成在第二半导体层中并与第二掩埋层的上部重叠; 选择性地形成在所述基底层中的所述第一导电类型的源极层; 以及形成在所述第一掩埋层上的所述基极层和所述第二半导体层上的栅电极，其间插入有栅极绝缘膜。

公开(公告)号：US20080315297A1

公开(公告)日：2008-12-25

申请号：US12144985

申请日：2008-06-24

申请人： Masakatsu TAKASHITA ,  Yasuto SUMI ,  Masaru IZUMISAWA ,  Hiroshi OHTA ,  Wataru SAITO ,  Syotaro ONO

发明人： Masakatsu TAKASHITA ,  Yasuto SUMI ,  Masaru IZUMISAWA ,  Hiroshi OHTA ,  Wataru SAITO ,  Syotaro ONO

IPC分类号： H01L29/78

CPC分类号： H01L21/26513 ,  H01L21/26586 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/32 ,  H01L29/402 ,  H01L29/66712 ,  H01L29/7811

摘要： There is provided a semiconductor device having a drift layer with a pillar structure including first semiconductor layer portions of the first conduction type and second semiconductor layer portions of the second conduction type formed in pillars alternately and periodically on a semiconductor substrate. A device region includes a plurality of arrayed transistors composed of the first semiconductor layer portions and the second semiconductor layer portions. A terminal region is formed at the periphery of the device region without the transistors formed therein. The drift layer in the terminal region has a carrier lifetime lower than ⅕ the carrier lifetime in the drift layer in the device region.

摘要翻译： 提供一种具有柱状结构的漂移层的半导体器件，其包括第一导电类型的第一半导体层部分和第二导电类型的第二半导体层部分在半导体衬底上交替周期地形成为柱状。 器件区域包括由第一半导体层部分和第二半导体层部分组成的多个阵列晶体管。 端子区域形成在器件区域的外围，而不形成晶体管。 端子区域中的漂移层的载流子寿命低于器件区域漂移层中的载流子寿命的1/5。

公开(公告)号：US20120068258A1

公开(公告)日：2012-03-22

申请号：US13052908

申请日：2011-03-21

申请人： Syotaro ONO ,  Wataru Saito ,  Shunji Taniuchi ,  Miho Watanabe ,  Hiroaki Yamashita

发明人： Syotaro ONO ,  Wataru Saito ,  Shunji Taniuchi ,  Miho Watanabe ,  Hiroaki Yamashita

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L29/7811 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/84 ,  H01L29/0619 ,  H01L29/402 ,  H01L29/42372 ,  H01L29/66712 ,  H01L2224/37013 ,  H01L2224/40245 ,  H01L2224/40479 ,  H01L2224/40499 ,  H01L2224/4103 ,  H01L2224/84203 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/37099

摘要： According to one embodiment, a semiconductor device includes a first main electrode, a control electrode, an extraction electrode, a second insulating film, a plurality of contact electrodes, and a control terminal. The first main electrode is electrically connected to a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type selectively provided on a surface of the first semiconductor region. The control electrode is provided on the first semiconductor region via a first insulating film. The extraction electrode is electrically connected to the control electrode. The second insulating film is provided on the first main electrode and the extraction electrode. The plurality of contact electrodes are provided in an inside of a plurality of first contact holes formed in the second insulating film and are electrically connected to the extraction electrode. The control terminal covers portions of the first main electrode provided on the first semiconductor region, on the second semiconductor region, and on the control electrode, respectively, and the extraction electrode, is electrically connected to the plurality of contact electrodes, and is electrically insulated from the first main electrode by the second insulating film.

摘要翻译： 根据一个实施例，半导体器件包括第一主电极，控制电极，引出电极，第二绝缘膜，多个接触电极和控制端子。 第一主电极电连接到第一导电类型的第一半导体区域和选择性地设置在第一半导体区域的表面上的第二导电类型的第二半导体区域。 控制电极经由第一绝缘膜设置在第一半导体区域上。 引出电极与控制电极电连接。 第二绝缘膜设置在第一主电极和引出电极上。 多个接触电极设置在形成在第二绝缘膜中的多个第一接触孔的内部，并与引出电极电连接。 控制端子分别覆盖设置在第一半导体区域上，第二半导体区域上和控制电极上的第一主电极的部分，并且引出电极电连接到多个接触电极，并且是电绝缘的 从第一主电极通过第二绝缘膜。

公开(公告)号：US20120074461A1

公开(公告)日：2012-03-29

申请号：US13235302

申请日：2011-09-16

申请人： Syotaro ONO ,  Wataru Saito ,  Shunji Taniuchi ,  Miho Watanabe ,  Hiroaki Yamashita

发明人： Syotaro ONO ,  Wataru Saito ,  Shunji Taniuchi ,  Miho Watanabe ,  Hiroaki Yamashita

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/331 ,  H01L29/739

CPC分类号： H01L29/7813 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/42376 ,  H01L29/4238

摘要： According to an embodiment, a semiconductor device includes a second semiconductor layer provided on a first semiconductor layer and including first pillars and second pillars. A first control electrode is provided in a trench of the second semiconductor layer and a second control electrode is provided on the second semiconductor layer and connected to the first control electrode. A first semiconductor region is provided on a surface of the second semiconductor layer except for a portion under the second control electrode. A second semiconductor region is provided on a surface of the first semiconductor region, the second semiconductor region being apart from the portion under the second control electrode and a third semiconductor region is provided on the first semiconductor region. A first major electrode is connected electrically to the first semiconductor layer and a second major electrode is connected electrically to the second and the third semiconductor region.

摘要翻译： 根据实施例，半导体器件包括设置在第一半导体层上并包括第一柱和第二柱的第二半导体层。 第一控制电极设置在第二半导体层的沟槽中，第二控制电极设置在第二半导体层上并连接到第一控制电极。 除了第二控制电极下方的部分之外，在第二半导体层的表面上设置第一半导体区域。 第二半导体区域设置在第一半导体区域的表面上，第二半导体区域与第二控制电极下方的部分分开，第三半导体区域设置在第一半导体区域上。 第一主电极与第一半导体层电连接，第二主电极与第二和第三半导体区域电连接。

公开(公告)号：US20130082261A1

公开(公告)日：2013-04-04

申请号：US13612200

申请日：2012-09-12

申请人： Wataru SAITO ,  Syotaro ONO ,  Toshiyuki NAKA ,  Shunji TANIUCHI ,  Hiroaki YAMASHITA

发明人： Wataru SAITO ,  Syotaro ONO ,  Toshiyuki NAKA ,  Shunji TANIUCHI ,  Hiroaki YAMASHITA

IPC分类号： H01L27/088

CPC分类号： H01L27/0629 ,  H01L27/0727 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/42372 ,  H01L29/7803 ,  H01L29/7804 ,  H01L29/7805 ,  H01L29/7806 ,  H01L29/7808 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/868 ,  H01L29/872

摘要： A semiconductor device comprising: a Metal Oxide Semiconductor Field Effect Transistor including: a semiconductor substrate including a first semiconductor layer of a first conductivity type; second semiconductor layers of a second conductivity type extending in a depth direction from one surface of the semiconductor substrate, and having space each other; a first diode including a fifth semiconductor layer of the second conductivity type contacting the second semiconductor layer in one surface side of the semiconductor substrate, the first semiconductor layer and the second semiconductor layers; and an anode of the second diode connected to an anode of the first diode.

摘要翻译： 一种半导体器件，包括：金属氧化物半导体场效应晶体管，包括：半导体衬底，包括第一导电类型的第一半导体层; 第二导电类型的第二半导体层，在深度方向上从半导体衬底的一个表面延伸并且彼此具有空间; 第一二极管，包括在半导体衬底的一个表面侧中与第二半导体层接触的第二导电类型的第五半导体层，第一半导体层和第二半导体层; 并且所述第二二极管的阳极连接到所述第一二极管的阳极。

公开(公告)号：US20090090968A1

公开(公告)日：2009-04-09

申请号：US12243280

申请日：2008-10-01

申请人： Syotaro ONO ,  Wataru Saito

发明人： Syotaro ONO ,  Wataru Saito

IPC分类号： H01L29/78

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/404

摘要： A semiconductor apparatus includes: a semiconductor layer of a first conductivity type; a first main electrode provided on a frontside of the semiconductor layer; a second main electrode provided on a backside of the semiconductor layer, the backside being opposite to the frontside; a plurality of semiconductor regions of a second conductivity type provided in a surface portion of the semiconductor layer in a edge termination region outside a device region in which a main current path is formed in a vertical direction between the first main electrode and the second main electrode; and a plurality of buried semiconductor regions of the second conductivity type provided in the semiconductor layer in the edge termination region, spaced from the semiconductor regions, and spaced from each other. The buried semiconductor regions provided substantially at the same depth from the frontside of the semiconductor layer are numbered as first, second, . . . , n-th, sequentially from the one nearer to the device region, the n-th buried semiconductor regions provided at different depths from the frontside of the semiconductor layer are displaced toward the device region relative to the corresponding n-th semiconductor region, and the buried semiconductor region located deeper from the frontside of the semiconductor layer is displaced more greatly toward the device region.

摘要翻译： 半导体装置包括：第一导电类型的半导体层; 设置在所述半导体层的前侧的第一主电极; 设置在所述半导体层的背面的第二主电极，所述背面与所述前侧相反; 在第一主电极和第二主电极之间沿垂直方向形成有主电流路径的器件区域外的边缘终端区域的半导体层的表面部分中设置的多个第二导电类型的半导体区域 ; 以及设置在边缘终端区域中的半导体层中的与半导体区域间隔开并且彼此间隔开的第二导电类型的多个掩埋半导体区域。 基本上与半导体层的前侧相同的深度设置的掩埋半导体区域被编号为第一，第二。 。 。 第n个从靠近器件区的一个顺序地，与半导体层的前侧不同的深度设置的第n个埋入半导体区域相对于相应的第n个半导体区域朝向器件区域移位， 位于半导体层的前侧较深的掩埋半导体区域朝向器件区域更大地移位。

公开(公告)号：US20080179671A1

公开(公告)日：2008-07-31

申请号：US12020288

申请日：2008-01-25

申请人： Wataru SAITO ,  Syotaro ONO

发明人： Wataru SAITO ,  Syotaro ONO

IPC分类号： H01L29/78

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/404

摘要： A semiconductor apparatus includes: a first first-conductivity-type semiconductor layer; a second first-conductivity-type semiconductor layer provided on a major surface of the first first-conductivity-type semiconductor layer in a device region and a termination region outside the device region; a third second-conductivity-type semiconductor layer being adjacent to the second first-conductivity-type semiconductor layer, forming a periodic array structure; a field insulating film provided on the second first-conductivity-type semiconductor layer and the third second-conductivity-type semiconductor layer in the termination region; a first field plate electrode provided on the field insulating film and connected to the second main electrode or the control electrode; and a second field plate electrode. The second field plate electrode partly overlies the first field plate electrode through intermediary of an insulating film and extends on the field insulating film outside the first field plate electrode. The second field plate electrode is floating in potential.

摘要翻译： 一种半导体装置，包括：第一第一导电型半导体层; 设置在器件区域中的第一第一导电型半导体层的主表面上的第二第一导电型半导体层和器件区域外的端接区域; 与第二第一导电型半导体层相邻的第三第二导电型半导体层，形成周期性阵列结构; 设置在终端区域中的第二第一导电型半导体层和第三第二导电型半导体层上的场绝缘膜; 设置在场绝缘膜上并连接到第二主电极或控制电极的第一场板电极; 和第二场板电极。 第二场板电极通过绝缘膜部分地覆盖在第一场极板电极上，并且在第一场极板电极外部的场绝缘膜上延伸。 第二场板电极浮置电位。