Semiconductor device
    1.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号:US08643091B2

    公开(公告)日:2014-02-04

    申请号:US13052028

    申请日:2011-03-18

    IPC分类号: H01L29/78 H01L21/336

    摘要: A semiconductor device includes first, second, third, and fourth semiconductor layers of alternating first and second conductivity types, an embedded electrode in a first trench that penetrates through the second semiconductor layer, a control electrode above the embedded electrode in the first trench, and first and second main electrodes. The fourth semiconductor layer is selectively provided in the first semiconductor layer and is connected to a lower end of a second trench, which penetrates through the second semiconductor layer. The first main electrode is electrically connected to the first semiconductor layer, and the second main electrode is in the second trench and electrically connected to the second, third, and fourth semiconductor layers. The embedded electrode is electrically connected to the second main electrode or the control electrode. A Shottky junction formed of the second main electrode and the first semiconductor layer is formed at a sidewall of the second trench.

    摘要翻译: 半导体器件包括交替的第一和第二导电类型的第一,第二,第三和第四半导体层,穿透第二半导体层的第一沟槽中的嵌入电极,在第一沟槽中的嵌入电极上方的控制电极,以及 第一和第二主电极。 第四半导体层选择性地设置在第一半导体层中,并且连接到穿过第二半导体层的第二沟槽的下端。 第一主电极与第一半导体层电连接,第二主电极位于第二沟槽中,并与第二,第三和第四半导体层电连接。 嵌入电极与第二主电极或控制电极电连接。 在第二沟槽的侧壁处形成由第二主电极和第一半导体层形成的肖特基结。

    SEMICONDUCTOR DEVICE
    3.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号:US20120241847A1

    公开(公告)日:2012-09-27

    申请号:US13424340

    申请日:2012-03-19

    IPC分类号: H01L29/78

    摘要: According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductive type, and a periodic array structure having a second semiconductor layer of a first conductive type and a third semiconductor layer of a second conductive type periodically arrayed on the first semiconductor layer in a direction parallel with a major surface of the first semiconductor layer. The second semiconductor layer and the third semiconductor layer are disposed in dots on the first semiconductor layer. A periodic structure in the outermost peripheral portion of the periodic array structure is different from a periodic structure of the periodic array structure in a portion other than the outermost peripheral portion.

    摘要翻译: 根据一个实施例,半导体器件包括第一导电类型的第一半导体层,以及周期性阵列结构,其具有第一导电类型的第二半导体层和周期性排列在第一半导体上的第二导电类型的第三半导体层 层在与第一半导体层的主表面平行的方向上。 第二半导体层和第三半导体层以点形式设置在第一半导体层上。 周期性阵列结构的最外围部分中的周期性结构不同于最外周部​​分以外的部分的周期性阵列结构的周期性结构。

    Semiconductor device
    4.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号:US08829608B2

    公开(公告)日:2014-09-09

    申请号:US13051987

    申请日:2011-03-18

    IPC分类号: H01L29/78

    摘要: According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type, a third semiconductor layer of a second conductivity type, a fourth semiconductor layer of the second conductivity type, a fifth semiconductor layer of the first conductivity type, a control electrode, a first main electrode, a second main electrode, and a sixth semiconductor layer of the first conductivity type. The second semiconductor layer and the third semiconductor layer are alternately provided on the first semiconductor layer in a direction substantially parallel to a major surface of the first semiconductor layer. The fourth semiconductor layer is provided on the second semiconductor layer and the third semiconductor layer. The fifth semiconductor layer is selectively provided on a surface of the fourth semiconductor layer. The control electrode is provided in a trench via an insulating film. The trench penetrates through the fourth semiconductor layer from a surface of the fifth semiconductor layer and is in contact with the second semiconductor layer. The first main electrode is connected to the first semiconductor layer. The second main electrode is connected to the fourth semiconductor layer and the fifth semiconductor layer. The sixth semiconductor layer is provided between the fourth semiconductor layer and the second semiconductor layer. An impurity concentration of the sixth semiconductor layer is higher than an impurity concentration of the second semiconductor layer.

    摘要翻译: 根据一个实施例,半导体器件包括第一导电类型的第一半导体层,第一导电类型的第二半导体层,第二导电类型的第三半导体层,第二导电类型的第四半导体层, 第一导电类型的第五半导体层,第一导电类型的控制电极,第一主电极,第二主电极和第六半导体层。 第二半导体层和第三半导体层在与第一半导体层的主表面大致平行的方向上交替地设置在第一半导体层上。 第四半导体层设置在第二半导体层和第三半导体层上。 第五半导体层选择性地设置在第四半导体层的表面上。 控制电极通过绝缘膜设置在沟槽中。 沟槽从第五半导体层的表面穿过第四半导体层并且与第二半导体层接触。 第一主电极连接到第一半导体层。 第二主电极连接到第四半导体层和第五半导体层。 第六半导体层设置在第四半导体层和第二半导体层之间。 第六半导体层的杂质浓度高于第二半导体层的杂质浓度。

    Semiconductor device
    6.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号:US08816410B2

    公开(公告)日:2014-08-26

    申请号:US13357381

    申请日:2012-01-24

    IPC分类号: H01L29/772

    摘要: A first semiconductor device of an embodiment includes a first semiconductor layer of a first conductivity type, a first control electrode, an extraction electrode, a second control electrode, and a third control electrode. The first control electrode faces a second semiconductor layer of the first conductivity type, a third semiconductor layer of a second conductivity type, and a fourth semiconductor layer of a first conductivity type, via a first insulating film. The second control electrode and the third control electrode are electrically connected to the extraction electrode, and face the second semiconductor layer under the extraction electrode, via the second insulating film. At least a part of the second control electrode and the whole of the third control electrode are provided under the extraction electrode. The electrical resistance of the second control electrode is higher than the electrical resistance of the third control electrode.

    摘要翻译: 实施例的第一半导体器件包括第一导电类型的第一半导体层,第一控制电极,引出电极,第二控制电极和第三控制电极。 第一控制电极通过第一绝缘膜面对第一导电类型的第二半导体层,第二导电类型的第三半导体层和第一导电类型的第四半导体层。 第二控制电极和第三控制电极通过第二绝缘膜电连接到引出电极,并且与提取电极下方的第二半导体层相对。 第二控制电极和整个第三控制电极的至少一部分设置在引出电极的下方。 第二控制电极的电阻高于第三控制电极的电阻。

    Power semiconductor device
    7.
    发明授权
    Power semiconductor device 有权
    功率半导体器件

    公开(公告)号:US08592893B2

    公开(公告)日:2013-11-26

    申请号:US13052893

    申请日:2011-03-21

    IPC分类号: H01L29/66

    摘要: According to one embodiment, a power semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type and a third semiconductor layer of a second conductivity type, a fourth semiconductor layer, a fifth semiconductor layer, a first and second main electrode, a first and second insulating film and a control electrode. The second and third layers are provided periodically on the first layer. The fourth layer is provided on the third layer. The fifth layer is selectively provided on the fourth layer. The first film is provided on sidewalls of a trench that reaches from a surface of the fifth layer to the second layer. The second film is provided closer to a bottom side of the trench than the first film and has a higher permittivity than the first film. The control electrode is embedded in the trench.

    摘要翻译: 根据一个实施例,功率半导体器件包括第一导电类型的第一半导体层,第一导电类型的第二半导体层和第二导电类型的第三半导体层,第四半导体层,第五半导体层, 第一和第二主电极,第一和第二绝缘膜和控制电极。 第二层和第三层周期性地设置在第一层上。 第四层设置在第三层上。 第五层选择性地设置在第四层上。 第一膜设置在从第五层的表面到第二层的沟槽的侧壁上。 第二膜比第一膜更靠近沟槽的底侧,并且具有比第一膜更高的介电常数。 控制电极嵌入沟槽中。

    SEMICONDUCTOR DEVICE
    9.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号:US20120012929A1

    公开(公告)日:2012-01-19

    申请号:US13051987

    申请日:2011-03-18

    IPC分类号: H01L29/78

    摘要: According to one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of the first conductivity type, a third semiconductor layer of a second conductivity type, a fourth semiconductor layer of the second conductivity type, a fifth semiconductor layer of the first conductivity type, a control electrode, a first main electrode, a second main electrode, and a sixth semiconductor layer of the first conductivity type. The second semiconductor layer and the third semiconductor layer are alternately provided on the first semiconductor layer in a direction substantially parallel to a major surface of the first semiconductor layer. The fourth semiconductor layer is provided on the second semiconductor layer and the third semiconductor layer. The fifth semiconductor layer is selectively provided on a surface of the fourth semiconductor layer. The control electrode is provided in a trench via an insulating film. The trench penetrates through the fourth semiconductor layer from a surface of the fifth semiconductor layer and is in contact with the second semiconductor layer. The first main electrode is connected to the first semiconductor layer. The second main electrode is connected to the fourth semiconductor layer and the fifth semiconductor layer. The sixth semiconductor layer is provided between the fourth semiconductor layer and the second semiconductor layer. An impurity concentration of the sixth semiconductor layer is higher than an impurity concentration of the second semiconductor layer.

    摘要翻译: 根据一个实施例,半导体器件包括第一导电类型的第一半导体层,第一导电类型的第二半导体层,第二导电类型的第三半导体层,第二导电类型的第四半导体层, 第一导电类型的第五半导体层,第一导电类型的控制电极,第一主电极,第二主电极和第六半导体层。 第二半导体层和第三半导体层在与第一半导体层的主表面大致平行的方向上交替地设置在第一半导体层上。 第四半导体层设置在第二半导体层和第三半导体层上。 第五半导体层选择性地设置在第四半导体层的表面上。 控制电极通过绝缘膜设置在沟槽中。 沟槽从第五半导体层的表面穿过第四半导体层并且与第二半导体层接触。 第一主电极连接到第一半导体层。 第二主电极连接到第四半导体层和第五半导体层。 第六半导体层设置在第四半导体层和第二半导体层之间。 第六半导体层的杂质浓度高于第二半导体层的杂质浓度。

    ELECTRIC POWER SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME
    10.
    发明申请
    ELECTRIC POWER SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME 有权
    电力半导体器件及其制造方法

    公开(公告)号:US20130221426A1

    公开(公告)日:2013-08-29

    申请号:US13600616

    申请日:2012-08-31

    IPC分类号: H01L21/336 H01L29/78

    摘要: A manufacturing method of an electric power semiconductor device includes following processes. A plurality of first second conductivity type impurity implantation layers are formed in a surface of a second semiconductor layer of a first conductivity type. A first trench is formed between a first non-implantation region and one of the plurality of first second conductivity type impurity implantation layers. An epitaxial layer of the first conductivity type is formed and covers the plurality of first second conductivity type impurity implantation layers. A plurality of second second conductivity type impurity implantation layers are formed in a surface of the epitaxial layer. A second trench is formed between a second non-implantation region and one of the plurality of second second conductivity type impurity implantation layers. A third semiconductor layer of the first conductivity type is formed and covers the plurality of second second conductivity type impurity implantation layers.

    摘要翻译: 电力半导体装置的制造方法包括以下处理。 在第一导电类型的第二半导体层的表面中形成多个第一第二导电型杂质注入层。 在第一非注入区域和多个第一第二导电型杂质注入层中的一个之间形成第一沟槽。 形成第一导电类型的外延层并覆盖多个第一第二导电型杂质注入层。 在外延层的表面形成多个第二第二导电型杂质注入层。 在第二非注入区域和多个第二第二导电型杂质注入层中的一个之间形成第二沟槽。 形成第一导电类型的第三半导体层并且覆盖多个第二第二导电型杂质注入层。