公开(公告)号：US4900952A

公开(公告)日：1990-02-13

申请号：US303778

申请日：1989-01-27

申请人： Shiro Hosotani ,  Takahiro Miki ,  Toshio Kumamoto

发明人： Shiro Hosotani ,  Takahiro Miki ,  Toshio Kumamoto

IPC分类号： G01R19/165 ,  H03K5/08 ,  H03K5/24

CPC分类号： H03K5/249

摘要： The voltage comparison apparatus of the invention features a timing control of clocks by which individual switches are ON/OFF controlled so that before a preceding amplifier circuit goes into comparison mode from auto zero mode, a successive amplifier circuit may go into auto zero mode from comparison mode, or before the preceding amplifier circuit goes into auto zero mode from comparison mode, the successive amplifier circuit may go into comparison mode from auto zero mode, whereby before the preceding amplifier circuit undergoes transition from the auto zero mode to the comparison mode, the successive amplifier circuit goes into the auto zero mode from the comparison mode, or before the preceding amplifier circuit undergoes transition from the comparison mode to the auto zero mode, the successive amplifier circuit goes into the comparison mode from the auto zero mode, and even when considerable variation occurs in input voltage difference during each clock cycle or clock time lags occurs, stable operation can be assured.

摘要翻译： 本发明的电压比较装置具有对各个开关进行ON / OFF控制的时钟的定时控制，使得在前一放大器电路从自动归零模式进入比较模式之前，连续的放大器电路可以从比较进入自动零模式 模式，或在比较模式之前的前一放大器电路进入自动归零模式之前，连续的放大器电路可以从自动调零模式进入比较模式，由此在之前的放大器电路经历从自动调零模式转换到比较模式之前， 连续放大器电路从比较模式进入自动归零模式，或者在前一放大器电路从比较模式转换到自动归零模式之前，连续放大器电路从自动归零模式进入比较模式，甚至当 在每个时钟周期或时钟时间滞后时，输入电压差异会发生相当大的变化 遏制，稳定运行可以放心。

公开(公告)号：US5283581A

公开(公告)日：1994-02-01

申请号：US952413

申请日：1992-09-29

申请人： Takahiro Miki ,  Toshio Kumamoto

发明人： Takahiro Miki ,  Toshio Kumamoto

IPC分类号： H03M1/14 ,  G06G7/14 ,  H03M1/16 ,  H03M1/74

CPC分类号： H03M1/167 ,  G06G7/14 ,  H03M1/747

摘要： An analog voltage subtracting circuit for calculating a difference between an analog input voltage and a voltage drop caused by a load includes an analog voltage generator 7 for generating an analog voltage, a load 3 having one end connected to an output of the analog voltage generator 7 and the other end connected to an output terminal 2, and a D/A converter 6 applying a positive output current Iout for generating a desired voltage drop at said the other end 4 of the load 3 and for applying a complementary output current Iout complementary to the positive output current Iout to said one end of the load 3. By this structure, a constant current of Iout+Iout flows at said one end 4 of the load 3, and therefore linear output can be provided.

摘要翻译： 用于计算模拟输入电压和由负载引起的电压降之间的差的模拟电压减去电路包括用于产生模拟电压的模拟电压发生器7，一端连接到模拟电压发生器7的输出的负载3 并且另一端连接到输出端子2和D / A转换器6，D / A转换器6施加正输出电流Iout，用于在负载3的另一端4处产生期望的电压降，并且用于施加互补的输出电流I ）与负载3的所述一端的正输出电流Iout互补。通过这种结构，Iout + I（OVS）的恒定电流在负载3的所述一端4处流动，因此可以提供线性输出。

公开(公告)号：US06069579A

公开(公告)日：2000-05-30

申请号：US131238

申请日：1998-08-07

申请人： Masao Ito ,  Takeshi Shigenobu ,  Toshio Kumamoto ,  Takahiro Miki ,  Hiroshi Komurasaki

发明人： Masao Ito ,  Takeshi Shigenobu ,  Toshio Kumamoto ,  Takahiro Miki ,  Hiroshi Komurasaki

IPC分类号： H03M1/14 ,  H03M1/20 ,  H03M1/36 ,  H03M1/12

CPC分类号： H03M1/205 ,  H03M1/141

摘要： An A/D converter simplifies its circuit configuration without deteriorating accuracy in A/D conversion. A circuit is formed of a folding and interpolation type. A gain-variable pre-amplifier group 11 amplifies each of reference voltages Vref1 to VrefN and an analog input voltage Vin, to output the result to a folding amplifier group 12, while a gain-variable pre-amplifier group 21 amplifies each of reference voltages Vrr1 to VrrJ and the analog input voltage Vin, to output the result to a comparator group 24. Each of pre-amplifiers constituting the gain-variable pre-amplifier groups 11 and 21 has an amplification factor that varies in upper and lower comparison periods according to a clock control signal .PHI.cnt.

摘要翻译： A / D转换器简化了其电路配置，而不会降低A / D转换的精度。 电路由折叠和内插形式组成。 增益可变前置放大器组11放大每个参考电压Vref1至VrefN和模拟输入电压Vin，以将结果输出到折叠放大器组12，而增益可变的前置放大器组21放大每个参考电压 Vrr1至VrrJ和模拟输入电压Vin，将结果输出到比较器组24.构成增益可变前置放大器组11和21的每个前置放大器具有在上和下比较周期内变化的放大系数， 到时钟控制信号PHI cnt。

公开(公告)号：US5625308A

公开(公告)日：1997-04-29

申请号：US557556

申请日：1995-11-14

申请人： Osamu Matsumoto ,  Takahiro Miki ,  Toshio Kumamoto

发明人： Osamu Matsumoto ,  Takahiro Miki ,  Toshio Kumamoto

IPC分类号： H03M1/34 ,  H03K3/0233 ,  H03K3/356 ,  H03K3/289

CPC分类号： H03K3/35606 ,  H03K3/356034 ,  H03K3/35613

摘要： A high-performance differential latch circuit which includes a differential amplifier circuit comprised of an NMOS transistor (27) serving as a constant current source, PMOS transistors (3, 4) and NMOS transistors (23,24), a latch circuit comprised of NMOS transistors (25, 26), and a switch circuit comprised of NMOS transistors (21,22,28) for alternately operating the differential amplifying function and latch function, the transistor (27) serving as the constant current source having a drain terminal directly connected to the transistors (23,24) and a source terminal directly connected to a ground voltage (2), whereby the differential latch circuit differentially amplifies the signals without the loss of the constant current source function during the differential amplification.

摘要翻译： 一种高性能差分锁存电路，包括由用作恒流源的NMOS晶体管（27），PMOS晶体管（3,4）和NMOS晶体管（23,24）组成的差分放大器电路，由NMOS 晶体管（25,26）以及由NMOS晶体管（21,22,28）组成的用于交替操作差分放大功能和锁存功能的开关电路，用作恒流源的晶体管（27）具有直接连接的漏极端子 到晶体管（23,24）和直接连接到接地电压（2）的源极端子，由此差分锁存电路在差分放大期间不损失恒定电流源功能而差分放大信号。

公开(公告)号：US5995031A

公开(公告)日：1999-11-30

申请号：US968207

申请日：1997-11-12

申请人： Takashi Okuda ,  Toshio Kumamoto ,  Masao Ito ,  Takahiro Miki

发明人： Takashi Okuda ,  Toshio Kumamoto ,  Masao Ito ,  Takahiro Miki

IPC分类号： H03M1/10 ,  H03M1/06 ,  H03M1/74 ,  H03M1/66

CPC分类号： H03M1/0663 ,  H03M1/747 ,  H03M3/464 ,  H03M3/502

摘要： A multi-bit D/A converter which improves the linearity of an analog output relative to a digital input is provided. A switch control circuit (1) turns on D some of a plurality of switches (S1 to SM) which are arranged in ascending order starting with a switch determined by a start position determination circuit (3) and turns off the remaining switches, the number of switches turned on being dependent on a digital signal (DIG). The start position determination circuit (3) sequentially changes the switches (S1, S3, S5, . . . ) serving as a selection start position to determine the selection start position for each input of the digital signal (DIG) provided in synchronism with a clock signal (CLK).

摘要翻译： 提供了一种提高模拟输出相对于数字输入的线性度的多位D / A转换器。 开关控制电路（1）接通D开始的开关位置确定电路（3）确定的开关的升序排列的多个开关（S1至SM）中的一些，并且关闭其余的开关 开关依赖于数字信号（DIG）。 开始位置确定电路（3）顺序地改变用作选择开始位置的开关（S1，S3，S5 ...），以确定与设置的与数字信号（DIG）同步的数字信号（DIG）的每个输入的选择开始位置 时钟信号（CLK）。

公开(公告)号：US5629700A

公开(公告)日：1997-05-13

申请号：US552016

申请日：1995-11-02

申请人： Toshio Kumamoto ,  Osamu Matsumoto ,  Takahiro Miki ,  Masao Ito ,  Takashi Okuda

发明人： Toshio Kumamoto ,  Osamu Matsumoto ,  Takahiro Miki ,  Masao Ito ,  Takashi Okuda

IPC分类号： H03M1/14 ,  H03M1/00 ,  H03M1/06 ,  H03M1/12 ,  H03M1/16 ,  H03M1/44 ,  H03M1/34

CPC分类号： H03M1/002 ,  H03M1/0682 ,  H03M1/069 ,  H03M1/1215 ,  H03M1/167

摘要： An A/D converter block A/D1 converts an analog input signal Vin to a digital signal and outputs its D/A output. First SH/SUBT7, 8 sample the signal Vin and a voltage VRM at the same timing with said A/D conversion and output the results of subtraction of the respective sampling values and the D/A output during holding, respectively. The both results of subtraction are several tens mV and there is no need of taking account of the linearity of a differential amplifier DIFF11. During the sampling, a circuit SHR1 outputs the differential voltages between each reference tap voltage taken out from specific 2 points of the ladder-type resistor in the A/D converter block A/D1 and the voltage VRM while a differential amplifier DIFF12 applies the reference voltages to the next A/D converter block A/D2. Such operations are performed in each stage. Thus, it becomes possible to make any S/H circuit and amplifier of excellent linearity in the first stage unnecessary to reduce the electric power consumption.

摘要翻译： A / D转换器模块A / D1将模拟输入信号Vin转换为数字信号并输出​​其D / A输出。 第一SH / SUBT7,8以与所述A / D转换相同的定时采样信号Vin和电压VRM，并分别输出相应采样值和保持期间的D / A输出的结果。 减法的结果都是几十mV，不需要考虑差分放大器DIFF11的线性度。 在采样期间，电路SHR1输出从A / D转换器模块A / D1中的梯形电阻器的特定2点取出的每个参考分接电压与电压VRM之间的差分电压，而差分放大器DIFF12施加参考 电压到下一个A / D转换器模块A / D2。 这样的操作在每个阶段进行。 因此，可以使得在第一级中具有优异线性度的任何S / H电路和放大器不必减少电力消耗。

公开(公告)号：US5341037A

公开(公告)日：1994-08-23

申请号：US886904

申请日：1992-05-22

申请人： Takahiro Miki ,  Toshio Kumamoto

发明人： Takahiro Miki ,  Toshio Kumamoto

IPC分类号： G11C27/02 ,  H03K5/159

CPC分类号： G11C27/026 ,  G11C27/024

摘要： Positive and negative output ends of a differential circuit in a sample hold circuit are connected to capacitors through switch circuits. Further, collectors of two input transistors of a buffer circuit connected to the sample hold circuit are driven by a collector driving differential circuit, so as to make the collector.multidot.base voltages of two input transistors same to each other. Consequently, a stable sample hold circuit having an arbitrary gain can be provided. In addition, drifts of outputs from two capacitors in the sample hold circuit can be made equal to each other by the buffer circuit.

摘要翻译： 采样保持电路中的差分电路的正和负输出端通过开关电路连接到电容器。 此外，连接到采样保持电路的缓冲电路的两个输入晶体管的集电极由集电极驱动差分电路驱动，以使两个输入晶体管的集电极基极彼此相同。 因此，可以提供具有任意增益的稳定的采样保持电路。 此外，可以通过缓冲电路将采样保持电路中的两个电容器的输出漂移相互相等。

公开(公告)号：US5936434A

公开(公告)日：1999-08-10

申请号：US912813

申请日：1997-08-19

申请人： Toshio Kumamoto ,  Masao Ito ,  Takahiro Miki ,  Takashi Okuda

发明人： Toshio Kumamoto ,  Masao Ito ,  Takahiro Miki ,  Takashi Okuda

IPC分类号： H03M1/34 ,  H03F3/45 ,  H03K5/08 ,  H03K5/24 ,  H03K5/153

CPC分类号： H03K5/249 ,  H03K5/2481

摘要： An object is to obtain a voltage comparator capable of high-accuracy voltage comparison. An input voltage (VIN) and a reference voltage (VREF) are connected to one electrode of a capacitor (C1) through switches (S1) and (S2), respectively. The other electrode of the capacitor (C1) is connected to the input portion of an inverter (INV1). The output portion of the inverter (INV1) is connected to the input portion of an inverter (INV3) and is also fed back to the input through a switch (S3). An inverter (INV11) is further connected in parallel with the inverter (INV1), wherein the input/output characteristics of the inverters (INV1, INV3 and INV11) are set equal.

摘要翻译： 目的是获得能够进行高精度电压比较的电压比较器。 分别通过开关（S1）和（S2）将输入电压（VIN）和参考电压（VREF）连接到电容器（C1）的一个电极。 电容器（C1）的另一个电极连接到逆变器（INV1）的输入部分。 逆变器（INV1）的输出部分连接到逆变器（INV3）的输入部分，并通过开关（S3）反馈到输入端。 反相器（INV11）进一步与反相器（INV1）并联连接，其中反相器（INV1，INV3和INV11）的输入/输出特性被设定为相等。

公开(公告)号：US5554989A

公开(公告)日：1996-09-10

申请号：US241422

申请日：1994-05-11

申请人： Toshio Kumamoto ,  Takahiro Miki

发明人： Toshio Kumamoto ,  Takahiro Miki

IPC分类号： H03M1/36 ,  H03M1/06

CPC分类号： H03M1/0682 ,  H03M1/368

摘要： Voltage comparators C.sub.1 -C.sub.N for comparing a first differential reference voltage obtained by dividing a first reference voltage V.sub.RT and a second reference voltage V.sub.RB by ladder resistors r.sub.1 -r.sub.N+1 and a second differential reference input voltage formed by a third voltage V.sub.i and a fourth voltage V.sub.i are arranged in first to N/2 and (N/2+1)-th to N-th voltage comparator rows in a folded manner and wiring area can be reduced as a result.

摘要翻译： 电压比较器C1-CN，用于比较通过用梯形电阻器r1-rN + 1划分第一参考电压VRT和第二参考电压VRB获得的第一差分参考电压和由第三电压Vi和第四电压形成的第二差分参考输入电压 电压+ E，ovs Vi + EE以折叠方式排列在第一至N / 2和（N / 2 + 1）至第N电压比较器行中，结果可以减少配线区域。

公开(公告)号：US5396131A

公开(公告)日：1995-03-07

申请号：US988599

申请日：1992-12-10

申请人： Takahiro Miki ,  Toshio Kumamoto

发明人： Takahiro Miki ,  Toshio Kumamoto

IPC分类号： H03F3/45 ,  H03K3/2885 ,  H03K5/08 ,  H03K5/24 ,  H03M1/14 ,  H03M1/34 ,  H03M1/36

CPC分类号： H03K3/2885 ,  H03K5/2418 ,  H03K5/2427 ,  H03M1/362

摘要： Disclosed is a high-speed A/D converter (15) including an improved differential amplifier circuit. Each comparator (61) provided in the A/D converter directly receives a complementary or differential analog input voltage to be converted. A differential amplifier circuit provided in each comparator compares an applied analog input voltage difference and an applied reference voltage difference. A binary signal indicative of a comparison result is applied to an encoder (4) through a binarization circuit. An analog input voltage which is not to be converted is directly applied to the comparator, that is, to the differential amplifier circuit through none of resistor elements and components, whereby conversion time delay is prevented.

摘要翻译： 公开了一种包括改进的差分放大器电路的高速A / D转换器（15）。 设置在A / D转换器中的每个比较器（61）直接接收待转换的互补或差分模拟输入电压。 在每个比较器中提供的差分放大器电路比较所施加的模拟输入电压差和施加的参考电压差。 指示比较结果的二进制信号通过二值化电路施加到编码器（4）。 将不转换的模拟输入电压直接施加到比较器，即不通过电阻元件和元件对差分放大器电路施加，从而防止转换时间延迟。