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30 条记录 (耗时 0.023 秒)

    Nonvolatile semiconductor memory device
    12.
    发明授权
    Nonvolatile semiconductor memory device 失效

    公开(公告)号：US06496427B2

    公开(公告)日：2002-12-17

    申请号：US09924998

    申请日：2001-08-08

    申请人： Makoto Kojima ,  Hisakazu Kotani

    发明人： Makoto Kojima ,  Hisakazu Kotani

    IPC分类号： G11C700

    CPC分类号： G11C29/848 ,  G11C16/08

    摘要： A nonvolatile semiconductor memory device with high repair efficiency prevents over-erasing even if a memory cell is replaced in the word line direction. The nonvolatile semiconductor memory device includes the following: erasing bias circuits for erasing data in normal memory cell arrays and a redundancy memory cell array; erasing decode circuits for decoding defective address information; and redundancy control circuits connected in series so that a preceding stage controls the next in order to store defective address information based on an erasing decode signal and to switch the erasing bias circuits based on the defective address information. In erasing data, the redundancy control circuits switch the erasing bias circuits so as to inhibit the application of an erasing bias to word and source lines connected to control gates of the normal memory cell array that is replaced by the redundant memory cell array and also inhibit the erasing bias application to those connected to control gates of the unused redundant memory cell array.

    Redundant memory cell selecting circuit having fuses coupled to memory cell group address and memory cell block address
    13.
    发明授权
    Redundant memory cell selecting circuit having fuses coupled to memory cell group address and memory cell block address 失效
    冗余存储单元选择电路具有耦合到存储单元组地址和存储单元块地址的熔丝

    公开(公告)号：US5953264A

    公开(公告)日：1999-09-14

    申请号：US937006

    申请日：1997-09-24

    申请人： Hiroshige Hirano ,  Hisakazu Kotani ,  Naomi Miyake

    发明人： Hiroshige Hirano ,  Hisakazu Kotani ,  Naomi Miyake

    IPC分类号： G11C29/00 ,  G11C29/24 ,  G11C13/00

    CPC分类号： G11C29/808 ,  G11C29/24 ,  G11C29/812 ,  G11C29/844

    摘要： An apparatus for selecting redundant memory cells in integrated circuit memory devices. The apparatus includes eight memory cell blocks, each of which includes a plurality of memory cell groups, a redundant memory cell group of a first set and a redundant memory cell group of a second set; and eight selecting fuse circuit blocks. Four of the selecting fuse circuit blocks are coupled to the memory cell blocks and adapted to select a redundant word line group of the first set of any of the eight memory cell blocks, and the other four selecting fuse circuit blocks are coupled to the memory cell blocks and adapted to select a redundant word line group of the second set of any of the eight memory cell blocks.

    摘要翻译： 一种用于在集成电路存储器件中选择冗余存储单元的装置。 该装置包括八个存储单元块，每个存储单元块包括多个存储单元组，第一组的冗余存储单元组和第二组的冗余存储单元组; 和八个选择熔丝电路块。 选择熔丝电路块中的四个耦合到存储单元块并且适于选择八个存储单元块中的任一个的第一组的冗余字线组，而另外四个选择熔丝电路块耦合到存储单元 并且适于选择八个存储器单元块中的任何一个的第二组的冗余字线组。

    Data transmission circuit, data line driving circuit, amplifying circuit, semiconductor integrated circuit, and semiconductor memory
    14.
    发明授权
    Data transmission circuit, data line driving circuit, amplifying circuit, semiconductor integrated circuit, and semiconductor memory 失效
    数据传输电路，数据线驱动电路，放大电路，半导体集成电路和半导体存储器

    公开(公告)号：US5680366A

    公开(公告)日：1997-10-21

    申请号：US573133

    申请日：1995-12-15

    申请人： Hisakazu Kotani ,  Hironori Akamatsu ,  Toshio Yamada ,  Akihiro Sawada ,  Hirohito Kikukawa ,  Masashi Agata ,  Shunichi Iwanari

    发明人： Hisakazu Kotani ,  Hironori Akamatsu ,  Toshio Yamada ,  Akihiro Sawada ,  Hirohito Kikukawa ,  Masashi Agata ,  Shunichi Iwanari

    IPC分类号： G11C5/02 ,  G11C7/10 ,  G11C11/4096 ,  H03K3/26

    CPC分类号： G11C7/1057 ,  G11C11/4096 ,  G11C5/025 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069

    摘要： In a driver circuit for driving a pair of data lines, the amplitude of a differential input signal is reduced from 2.5 V to 0.6 V, which is smaller than a conventional lower-limit source voltage (approximately 1.5 V). The amplitude of the differential signal transmitted through the pair of data lines is amplified to 2.5 V by an amplifying circuit and the resulting signal is then latched by a latch circuit. After the latching by the latch circuit, the operation of the amplifying circuit is halted. The driver circuit is constituted solely by a plurality of NMOS transistors so as not to increase a leakage current flowing in the off state. Here, the threshold voltage of the NMOS transistor positioned on the ground side is reduced to a conventional lower-limit value (0.3 V to 0.6 V), while the threshold voltage of the NMOS transistor on the power-source side to a value lower than the above lower-limit value (0 V to 0.3 V), thereby enhancing a driving force of the NMOS transistor on the power-source side.

    摘要翻译： 在用于驱动一对数据线的驱动电路中，差分输入信号的幅度从2.5V减小到小于常规下限电源电压（约1.5V）的0.6V。 通过一对数据线传输的差分信号的幅度被放大电路放大到2.5V，然后由锁存电路锁存所得到的信号。 在锁存电路锁存之后，停止放大电路的工作。 驱动电路仅由多个NMOS晶体管构成，以便不增加在断开状态下流动的漏电流。 这里，位于地侧的NMOS晶体管的阈值电压降低到常规的下限值（0.3V〜0.6V），而电源侧的NMOS晶体管的阈值电压低于 上述下限值（0V至0.3V），从而增强了在电源侧的NMOS晶体管的驱动力。

    SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR DEVICE
    17.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR DEVICE 有权
    半导体存储器件和半导体器件

    公开(公告)号：US20080313391A1

    公开(公告)日：2008-12-18

    申请号：US12136340

    申请日：2008-06-10

    申请人： Shunichi Iwanari ,  Hisakazu Kotani ,  Masanori Matsuura

    发明人： Shunichi Iwanari ,  Hisakazu Kotani ,  Masanori Matsuura

    IPC分类号： G06F12/02

    CPC分类号： G11C16/26 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1063

    摘要： A semiconductor memory device, including: a cell array block including a plurality of memory cells arranged therein; and a controller, wherein the controller controls the semiconductor memory device so that: an operation of reading out data from a second region in the cell array block is initiated before completion of an operation of outputting data read out from a first region in the cell array block; and the data read out from the second region is output successively after the completion of the operation of outputting data read out from the first region.

    摘要翻译： 一种半导体存储器件，包括：包括布置在其中的多个存储单元的单元阵列块; 以及控制器，其中所述控制器控制所述半导体存储器件，使得：在完成从所述单元阵列中的第一区域读出的数据的输出的操作完成之前，开始从所述单元阵列块中的第二区域读出数据的操作 块; 在从第一区域读出的数据的输出操作完成之后连续地输出从第二区域读出的数据。

    Semiconductor memory, moving-picture storing memory, moving-picture storing apparatus, moving-picture displaying apparatus, static-picture storing memory, and electronic notebook
    18.
    发明授权
    Semiconductor memory, moving-picture storing memory, moving-picture storing apparatus, moving-picture displaying apparatus, static-picture storing memory, and electronic notebook 失效
    半导体存储器，运动图像存储存储器，运动图像存储装置，运动图像显示装置，静态图像存储存储器和电子笔记本

    公开(公告)号：US6023440A

    公开(公告)日：2000-02-08

    申请号：US320577

    申请日：1999-05-27

    申请人： Hisakazu Kotani ,  Hironori Akamatsu ,  Tsutomu Fujita

    发明人： Hisakazu Kotani ,  Hironori Akamatsu ,  Tsutomu Fujita

    IPC分类号： G09G5/39 ,  G11C11/406 ,  G11C13/00

    CPC分类号： G09G5/39 ,  G11C11/406 ,  G09G2360/123 ,  G09G5/001

    摘要： A memory array divided into a plurality of sub-memory-arrays is disposed on a chip so that, if a specified sub-memory-array is selected by a sub-memory-array selecting circuit, a normal read/write operation is performed with respect to the sub-memory-array based on an address indicated by a group of external address signals. At the same time, a clock generator for self-refresh mounted on a chip generates a word-line basic clock for self-refresh and a word-line basic clock for refresh, thereby selecting the word lines in the sub-memory-arrays which have not been selected. Prior to a predetermined time at which the sub-memory-array subjected to a refresh operation is subsequently selected, a refresh halt signal is outputted so as to forcibly halt the refresh operation, thereby preventing insufficient recharging of a memory cell. Each of the plurality of sub-memory-arrays stores, of sequential sets of image data, data on one frame or one field.

    摘要翻译： 分割成多个子存储器阵列的存储器阵列设置在芯片上，使得如果通过子存储器阵列选择电路选择了指定的子存储器阵列，则执行正常的读取/写入操作， 基于由一组外部地址信号指示的地址对子存储器阵列。 同时，安装在芯片上的用于自刷新的时钟发生器产生用于自刷新的字线基本时钟和用于刷新的字线基本时钟，从而选择子存储阵列中的字线，其中 尚未选中。 在随后选择进行刷新操作的子存储阵列的预定时间之前，输出刷新停止信号，以强制中止刷新操作，从而防止存储单元的充电不足。 多个子存储器阵列中的每一个存储顺序的图像数据组，一帧或一个场上的数据。