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    Nonvolatile semiconductor memory device
    1.
    发明授权
    Nonvolatile semiconductor memory device 失效

    公开(公告)号：US06496427B2

    公开(公告)日：2002-12-17

    申请号：US09924998

    申请日：2001-08-08

    申请人： Makoto Kojima ,  Hisakazu Kotani

    发明人： Makoto Kojima ,  Hisakazu Kotani

    IPC分类号： G11C700

    CPC分类号： G11C29/848 ,  G11C16/08

    摘要： A nonvolatile semiconductor memory device with high repair efficiency prevents over-erasing even if a memory cell is replaced in the word line direction. The nonvolatile semiconductor memory device includes the following: erasing bias circuits for erasing data in normal memory cell arrays and a redundancy memory cell array; erasing decode circuits for decoding defective address information; and redundancy control circuits connected in series so that a preceding stage controls the next in order to store defective address information based on an erasing decode signal and to switch the erasing bias circuits based on the defective address information. In erasing data, the redundancy control circuits switch the erasing bias circuits so as to inhibit the application of an erasing bias to word and source lines connected to control gates of the normal memory cell array that is replaced by the redundant memory cell array and also inhibit the erasing bias application to those connected to control gates of the unused redundant memory cell array.

    Semiconductor memory device and semiconductor device
    2.
    发明授权
    Semiconductor memory device and semiconductor device 有权
    半导体存储器件和半导体器件

    公开(公告)号：US07991945B2

    公开(公告)日：2011-08-02

    申请号：US12136340

    申请日：2008-06-10

    申请人： Shunichi Iwanari ,  Hisakazu Kotani ,  Masanori Matsuura

    发明人： Shunichi Iwanari ,  Hisakazu Kotani ,  Masanori Matsuura

    IPC分类号： G06F13/00 ,  G06F13/28 ,  G11C7/00

    CPC分类号： G11C16/26 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1063

    摘要： A semiconductor memory device, including: a cell array block including a plurality of memory cells arranged therein; and a controller, wherein the controller controls the semiconductor memory device so that: an operation of reading out data from a second region in the cell array block is initiated before completion of an operation of outputting data read out from a first region in the cell array block; and the data read out from the second region is output successively after the completion of the operation of outputting data read out from the first region.

    摘要翻译： 一种半导体存储器件，包括：包括布置在其中的多个存储单元的单元阵列块; 以及控制器，其中所述控制器控制所述半导体存储器件，使得：在完成从所述单元阵列中的第一区域读出的数据的输出的操作完成之前，开始从所述单元阵列块中的第二区域读出数据的操作 块; 在从第一区域读出的数据的输出操作完成之后连续地输出从第二区域读出的数据。

    Semiconductor apparatus including a switch element and resistance element connected in series
    3.
    发明授权
    Semiconductor apparatus including a switch element and resistance element connected in series 失效
    包括串联连接的开关元件和电阻元件的半导体装置

    公开(公告)号：US07030639B2

    公开(公告)日：2006-04-18

    申请号：US10776237

    申请日：2004-02-12

    申请人： Masahiro Ueminami ,  Hisakazu Kotani ,  Katsuhiko Shishido

    发明人： Masahiro Ueminami ,  Hisakazu Kotani ,  Katsuhiko Shishido

    IPC分类号： G01R31/26

    CPC分类号： G01R31/2853 ,  H01L22/34 ,  H01L2224/05554 ,  H01L2224/48145 ,  H01L2224/49175 ,  H01L2924/13091 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2924/00012

    摘要： A semiconductor apparatus includes serially-connected bodies composed of a switch element and a resistance element respectively interposed between terminals adjacent to one another, conduction-test terminals connected to one and another ends of a series of the serially-connected bodies, and a switch control terminal for collectively controlling all the plural switch elements. Also included are switch elements interposed alternately on the first semiconductor chip side and the second semiconductor chip side between wires adjacent to one another, conduction-test terminals connected to one and another ends of a series of the serially-connected switch elements, and a switch control terminal for collectively controlling all the plural switch elements.

    摘要翻译： 一种半导体装置，包括：串联连接体，分别插在彼此相邻的端子之间的开关元件和电阻元件;连接到一系列串联体的一端和另一端的导通测试端子，以及开关控制 用于集体控制所有多个开关元件的端子。 还包括在第一半导体芯片侧交替设置的开关元件和彼此相邻的布线之间的第二半导体芯片侧，连接到一系列串联连接的开关元件的一端和另一端的导通测试端子，以及开关 用于集体控制所有多个开关元件的控制端子。

    Divided wordline memory arrangement having overlapping activation of wordlines during continuous access cycle
    5.
    发明授权
    Divided wordline memory arrangement having overlapping activation of wordlines during continuous access cycle 失效
    分割的字线存储器布置在连续访问周期期间具有字线重叠的激活

    公开(公告)号：US5699300A

    公开(公告)日：1997-12-16

    申请号：US341947

    申请日：1994-11-16

    申请人： Hironori Akamatsu ,  Tsuyoshi Shiragasawa ,  Junko Matsushima ,  Hisakazu Kotani

    发明人： Hironori Akamatsu ,  Tsuyoshi Shiragasawa ,  Junko Matsushima ,  Hisakazu Kotani

    IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C8/14 ,  G11C8/18 ,  G11C11/409 ,  G11C7/00 ,  G11C8/00

    CPC分类号： G11C7/1015 ,  G11C8/14 ,  G11C8/18

    摘要： A semiconductor memory device comprising memory cells arranged in a matrix with plural pairs of bit lines to be column addressed and connected to sense amplifiers, and word lines to be row addressed and divided into divisional word lines. Output signals of sense amplifiers selected by the column addressing are transferred to respective data lines. The divisional word lines are time-sequentially activated corresponding to the row addressing with the activated states of any two sequential divisional word lines overlapped for a fractional time of the full activation time. The sense amplifiers are grouped into plural groups with respective common column addresses. Each group of sense amplifiers have their outputs to be applied to respective data lines connected to a serial/parallel converter.

    摘要翻译： 一种半导体存储器件，包括以矩阵形式布置的存储器单元，其中多对位线被列地址并连接到读出放大器，并且字线被行寻址并分成划分字线。 由列寻址选择的读出放大器的输出信号被传送到相应的数据线。 分割字线对应于行寻址而被时间顺序地激活，其中任何两个连续分割字线的激活状态在完全激活时间的分数时间内重叠。 感测放大器被分组成具有相应公共列地址的多个组。 每组读出放大器的输出都被施加到连接到串行/并行转换器的相应数据线上。

    Static random access memory capable of reducing stendly power consumption and off-leakage current
    8.
    发明授权
    Static random access memory capable of reducing stendly power consumption and off-leakage current 失效
    静态随机存取存储器能够降低待机功耗和漏电流

    公开(公告)号：US5764566A

    公开(公告)日：1998-06-09

    申请号：US893682

    申请日：1997-07-11

    申请人： Hironori Akamatsu ,  Toru Iwata ,  Hisakazu Kotani

    发明人： Hironori Akamatsu ,  Toru Iwata ,  Hisakazu Kotani

    IPC分类号： G11C11/412 ,  G11C11/417 ,  G11C11/413

    CPC分类号： G11C11/412 ,  G11C11/417

    摘要： When a memory chip is in a standby mode, a ground power supply line of a flip-flop forming a memory cell is intermittently placed in the floating state. A switching NMOS transistor is connected between the ground power supply line and a power supply VSS. The gate of the NMOS transistor is controlled by an activation signal. When entering the floating state, the ground power supply line is charged due to an off-leakage current flowing in the transistor of the memory cell. As a result, the voltage of the ground power supply line is increased from the voltage of the power supply VSS. Accordingly, the off-leakage current of the memory cell is reduced, whereby the standby-time power consumption of the memory chip is decreased. When the voltage of the ground power supply line keeps going up, it becomes impossible to read data held in the memory cell in a short time, resulting in the data being lost. In order to prevent the loss of the data, the switching NMOS transistor is made to intermittently turn on.

    摘要翻译： 当存储器芯片处于待机模式时，形成存储单元的触发器的接地电源线被间歇地置于浮置状态。 开关NMOS晶体管连接在接地电源线和电源VSS之间。 NMOS晶体管的栅极由激活信号控制。 当进入浮动状态时，由于在存储单元的晶体管中流过的漏电流导致接地电源线被充电。 结果，接地电源线的电压从电源VSS的电压增加。 因此，存储单元的泄漏电流减小，从而存储芯片的待机时功耗降低。 当接地电源线的电压持续上升时，不可能在短时间内读取保存在存储单元中的数据，导致数据丢失。 为了防止数据丢失，使开关式NMOS晶体管间歇地导通。

    Redundant memory cell selecting circuit having fuses coupled to memory cell group address and memory cell block address
    10.
    发明授权
    Redundant memory cell selecting circuit having fuses coupled to memory cell group address and memory cell block address 失效
    冗余存储单元选择电路具有耦合到存储单元组地址和存储单元块地址的熔丝

    公开(公告)号：US5953264A

    公开(公告)日：1999-09-14

    申请号：US937006

    申请日：1997-09-24

    申请人： Hiroshige Hirano ,  Hisakazu Kotani ,  Naomi Miyake

    发明人： Hiroshige Hirano ,  Hisakazu Kotani ,  Naomi Miyake

    IPC分类号： G11C29/00 ,  G11C29/24 ,  G11C13/00

    CPC分类号： G11C29/808 ,  G11C29/24 ,  G11C29/812 ,  G11C29/844

    摘要： An apparatus for selecting redundant memory cells in integrated circuit memory devices. The apparatus includes eight memory cell blocks, each of which includes a plurality of memory cell groups, a redundant memory cell group of a first set and a redundant memory cell group of a second set; and eight selecting fuse circuit blocks. Four of the selecting fuse circuit blocks are coupled to the memory cell blocks and adapted to select a redundant word line group of the first set of any of the eight memory cell blocks, and the other four selecting fuse circuit blocks are coupled to the memory cell blocks and adapted to select a redundant word line group of the second set of any of the eight memory cell blocks.

    摘要翻译： 一种用于在集成电路存储器件中选择冗余存储单元的装置。 该装置包括八个存储单元块，每个存储单元块包括多个存储单元组，第一组的冗余存储单元组和第二组的冗余存储单元组; 和八个选择熔丝电路块。 选择熔丝电路块中的四个耦合到存储单元块并且适于选择八个存储单元块中的任一个的第一组的冗余字线组，而另外四个选择熔丝电路块耦合到存储单元 并且适于选择八个存储器单元块中的任何一个的第二组的冗余字线组。