公开(公告)号：US09368498B2

公开(公告)日：2016-06-14

申请号：US14878012

申请日：2015-10-08

Applicant: IMEC VZW

Inventor： Geert Eneman ,  Benjamin Vincent ,  Voon Yew Thean

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/78 ,  H01L21/8238

CPC classification number: H01L27/0886 ,  H01L21/823821 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7842 ,  H01L29/7849

Abstract: A FinFET device and a method for manufacturing a FinFET device is provided. An example device may comprise a substrate including at least two fin structures. Each of the at least two fin structures may be in contact with a source and drain region and each of the at least two fin structures may include a strain relaxed buffer (SRB) overlying and in contact with the substrate and an upper layer overlying and in contact with the SRB. The composition of the upper layer and the SRB may be selected such that the upper layer of a first fin structure is subjected to a first mobility enhancing strain in the as-grown state, the first mobility enhancing strain being applied in a longitudinal direction from the source region to the drain region and where at least an upper part of the upper layer of a second fin structure is strain-relaxed.

公开(公告)号：US08963225B2

公开(公告)日：2015-02-24

申请号：US14024820

申请日：2013-09-12

Applicant: IMEC ,  GLOBALFOUNDRIES Inc.

Inventor： Benjamin Vincent ,  Geert Hellings ,  David Paul Brunco

IPC: H01L29/94 ,  H01L21/336

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/0257 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/785 ,  H01L29/7856

Abstract: The disclosure is related to a band engineered semiconductor device comprising a substrate, a protruding structure that is formed in a recess in the substrate and is extending above the recess having a buried portion and an extended portion, and wherein at least the extended portion comprises a semiconductor material having an inverted ‘V’ band gap profile with a band gap value increasing gradually from a first value at lateral edges of the structure to a second value, higher than the first value, in a center of the structure. The disclosure is also related to the method of manufacturing of such band engineered semiconductor device.

Abstract translation: 本发明涉及一种带状工程半导体器件，其包括衬底，突出结构，其形成在衬底中的凹部中并且在凹部上方延伸，具有掩埋部分和延伸部分，并且其中至少延伸部分包括 具有倒置“V”带隙分布的半导体材料，带隙值从该结构的横向边缘处的第一值逐渐增加到高于该结构的中心的第二值。 本发明还涉及这种带状工程半导体器件的制造方法。

公开(公告)号：US20140024204A1

公开(公告)日：2014-01-23

申请号：US13944592

申请日：2013-07-17

Applicant: IMEC

Inventor： Andriy Hikavyy ,  Benjamin Vincent ,  Roger Loo

IPC: H01L21/02

CPC classification number: H01L21/02636 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/2053

Abstract: Disclosed are methods for selective deposition of doped Group IV-Sn materials. In some embodiments, the method includes providing a patterned substrate comprising at least a first region and a second region, where the first region includes an exposed first semiconductor material and the second region includes an exposed insulator material, and performing at least two cycles of a grow-etch cyclic process. Each cycle includes depositing a doped Group IV-Tin (Sn) layer, where depositing the doped Group IV-Sn layer includes providing a Group IV precursor, a Sn precursor, and a dopant precursor, and using an etch gas to etch back the deposited doped Group IV-Sn layer.

Abstract translation: 公开了用于选择性沉积掺杂的IV-Sn族材料的方法。 在一些实施例中，该方法包括提供包括至少第一区域和第二区域的图案化衬底，其中第一区域包括暴露的第一半导体材料，并且第二区域包括暴露的绝缘体材料，并且执行至少两个循环 生长蚀刻循环过程。 每个循环包括沉积掺杂的IV族锡（Sn）层，其中沉积掺杂的IV-Sn层包括提供IV族前体，Sn前体和掺杂剂前体，并使用蚀刻气体来回蚀刻沉积 掺杂IV-Sn层。

公开(公告)号：US20170040168A1

公开(公告)日：2017-02-09

申请号：US15333995

申请日：2016-10-25

Applicant: IMEC

Inventor： Benjamin Vincent ,  Voon Yew Thean ,  Liesbeth Witters

IPC: H01L21/02 ,  C30B25/04 ,  H01L29/78 ,  H01L21/762 ,  H01L29/66 ,  H01L29/06 ,  C30B23/04 ,  C30B19/12

CPC classification number: H01L21/02639 ,  C30B19/00 ,  C30B19/12 ,  C30B23/04 ,  C30B25/04 ,  H01L21/02381 ,  H01L21/02422 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02647 ,  H01L21/02664 ,  H01L21/762 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7851

Abstract: Disclosed are methods and mask structures for epitaxially growing substantially defect-free semiconductor material. In some embodiments, mask structure includes a first level defining a first trench extending through the first level, wherein a bottom of the first trench is defined by a semiconductor substrate, and a second level on top of the first level, wherein the second level defines a plurality of second trenches positioned at a non-zero angle with respect to the first trench.

Abstract translation: 公开了用于外延生长基本上无缺陷的半导体材料的方法和掩模结构。 在一些实施例中，掩模结构包括限定延伸穿过第一层的第一沟槽的第一层，其中第一沟槽的底部由半导体衬底限定，第二层位于第一层的顶部，其中第二层限定 多个相对于第一沟槽非零角度定位的第二沟槽。

公开(公告)号：US09476143B2

公开(公告)日：2016-10-25

申请号：US13768462

申请日：2013-02-15

Applicant: IMEC

Inventor： Benjamin Vincent ,  Voon Yew Thean ,  Liesbeth Witters

IPC: C30B25/04 ,  C30B23/04 ,  H01L21/02 ,  H01L29/66 ,  C30B19/00

CPC classification number: H01L21/02639 ,  C30B19/00 ,  C30B19/12 ,  C30B23/04 ,  C30B25/04 ,  H01L21/02381 ,  H01L21/02422 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02647 ,  H01L21/02664 ,  H01L21/762 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/7851

Abstract: Disclosed are methods and mask structures for epitaxially growing substantially defect-free semiconductor material. In some embodiments, the method may comprise providing a substrate comprising a first crystalline material, where the first crystalline material has a first lattice constant; providing a mask structure on the substrate, where the mask structure comprises a first level comprising a first opening extending through the first level (where a bottom of the first opening comprises the substrate), and a second level on top of the first level, where the second level comprises a plurality of second trenches positioned at a non-zero angle with respect to the first opening. The method may further comprise epitaxially growing a second crystalline material on the bottom of the first opening, where the second crystalline material has a second lattice constant different than the first lattice constant and defects in the second crystalline material are trapped in the first opening.

Abstract translation: 公开了用于外延生长基本上无缺陷的半导体材料的方法和掩模结构。 在一些实施例中，该方法可以包括提供包括第一晶体材料的基底，其中第一晶体材料具有第一晶格常数; 在所述衬底上提供掩模结构，其中所述掩模结构包括第一层，所述第一层包括延伸穿过所述第一层的第一开口（其中所述第一开口的底部包括所述衬底），以及在所述第一层的顶部上的第二层， 第二级包括相对于第一开口非零角度定位的多个第二沟槽。 该方法还可以包括在第一开口的底部上外延生长第二晶体材料，其中第二晶体材料具有不同于第一晶格常数的第二晶格常数，并且第二晶体材料中的缺陷被捕获在第一开口中。

公开(公告)号：US09263263B2

公开(公告)日：2016-02-16

申请号：US13944592

申请日：2013-07-17

Applicant: IMEC

Inventor： Andriy Hikavyy ,  Benjamin Vincent ,  Roger Loo

IPC: H01L21/02 ,  H01L21/205

CPC classification number: H01L21/02636 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/2053

Abstract: Disclosed are methods for selective deposition of doped Group IV-Sn materials. In some embodiments, the method includes providing a patterned substrate comprising at least a first region and a second region, where the first region includes an exposed first semiconductor material and the second region includes an exposed insulator material, and performing at least two cycles of a grow-etch cyclic process. Each cycle includes depositing a doped Group IV-Tin (Sn) layer, where depositing the doped Group IV-Sn layer includes providing a Group IV precursor, a Sn precursor, and a dopant precursor, and using an etch gas to etch back the deposited doped Group IV-Sn layer.

Abstract translation: 公开了用于选择性沉积掺杂的IV-Sn族材料的方法。 在一些实施例中，该方法包括提供包括至少第一区域和第二区域的图案化衬底，其中第一区域包括暴露的第一半导体材料，并且第二区域包括暴露的绝缘体材料，并且执行至少两个循环 生长蚀刻循环过程。 每个循环包括沉积掺杂的IV族锡（Sn）层，其中沉积掺杂的IV-Sn层包括提供IV族前体，Sn前体和掺杂剂前体，并使用蚀刻气体来回蚀刻沉积 掺杂IV-Sn层。

公开(公告)号：US09117777B2

公开(公告)日：2015-08-25

申请号：US14106699

申请日：2013-12-13

Applicant: IMEC

Inventor： Benjamin Vincent ,  Geert Eneman

IPC: H01L21/322 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L21/3225 ,  H01L21/02532 ,  H01L21/02694 ,  H01L21/762 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for reducing defects from an active layer is disclosed. The active layer may be part of a semiconductor in a semiconductor device. The active layer may be defined at least laterally by an isolation structure, and may physically contact an isolation structure at a contact interface. The isolation structure and the active layer may abut on a common substantially planar surface. The method may include providing a patterned stress-inducing layer on the common substantially planar surface. The stress-inducing layer may be adapted for inducing a stress field in the active layer, and induced stress field may result in a shear stress on a defect in the active layer. The method may also include performing an anneal step after providing the patterned stress-inducing layer on the common substantially planar surface. The method may additionally include removing the patterned stress-inducing layer from the common substantially planar surface.

Abstract translation: 公开了一种用于从有源层减少缺陷的方法。 有源层可以是半导体器件中的半导体的一部分。 有源层可以至少由隔离结构侧向限定，并且可以在接触界面物理地接触隔离结构。 隔离结构和有源层可以邻接在共同的基本平坦的表面上。 该方法可以包括在共同的基本上平坦的表面上提供图案化的应力诱导层。 应力诱导层可以适于在活性层中诱导应力场，并且感应应力场可能导致活性层中缺陷的剪切应力。 该方法还可以包括在将图案化的应力诱导层提供在共同的基本平坦的表面上之后执行退火步骤。 该方法可以另外包括从共同的基本平坦的表面去除图案化的应力诱导层。