公开(公告)号：US09263263B2

公开(公告)日：2016-02-16

申请号：US13944592

申请日：2013-07-17

Applicant: IMEC

Inventor： Andriy Hikavyy ,  Benjamin Vincent ,  Roger Loo

IPC: H01L21/02 ,  H01L21/205

CPC classification number: H01L21/02636 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/2053

Abstract: Disclosed are methods for selective deposition of doped Group IV-Sn materials. In some embodiments, the method includes providing a patterned substrate comprising at least a first region and a second region, where the first region includes an exposed first semiconductor material and the second region includes an exposed insulator material, and performing at least two cycles of a grow-etch cyclic process. Each cycle includes depositing a doped Group IV-Tin (Sn) layer, where depositing the doped Group IV-Sn layer includes providing a Group IV precursor, a Sn precursor, and a dopant precursor, and using an etch gas to etch back the deposited doped Group IV-Sn layer.

Abstract translation: 公开了用于选择性沉积掺杂的IV-Sn族材料的方法。 在一些实施例中，该方法包括提供包括至少第一区域和第二区域的图案化衬底，其中第一区域包括暴露的第一半导体材料，并且第二区域包括暴露的绝缘体材料，并且执行至少两个循环 生长蚀刻循环过程。 每个循环包括沉积掺杂的IV族锡（Sn）层，其中沉积掺杂的IV-Sn层包括提供IV族前体，Sn前体和掺杂剂前体，并使用蚀刻气体来回蚀刻沉积 掺杂IV-Sn层。

公开(公告)号：US10361268B2

公开(公告)日：2019-07-23

申请号：US15907878

申请日：2018-02-28

Applicant: IMEC VZW

Inventor： Kurt Wostyn ,  Hans Mertens ,  Liesbeth Witters ,  Andriy Hikavyy ,  Naoto Horiguchi

IPC: H01L29/06 ,  H01L29/66 ,  B82Y40/00 ,  H01L21/8234 ,  H01L29/08 ,  B82Y10/00 ,  H01L29/417 ,  H01L29/775 ,  H01L21/311

Abstract: A method of forming an internal spacer between nanowires, the method involving: providing a fin comprising a stack of layers of sacrificial material alternated with nanowire material, and selectively removing part of the sacrificial material, thereby forming a recess. The method also involves depositing dielectric material into the recess resulting in dielectric material within the recess and excess dielectric material outside the recess, where a crevice remains in the dielectric material in each recess, and removing the excess dielectric material using a first etchant. The method also involves enlarging the crevices to form a gap using a second etchant such that a remaining dielectric material still covers the sacrificial material and partly covers the nanowire material, and such that outer ends of the nanowire material are accessible; and growing electrode material on the outer ends such that the electrode material from neighboring outer ends merge, thereby covering the gap.

公开(公告)号：US20180254321A1

公开(公告)日：2018-09-06

申请号：US15907878

申请日：2018-02-28

Applicant: IMEC VZW

Inventor： Kurt Wostyn ,  Hans Mertens ,  Liesbeth Witters ,  Andriy Hikavyy ,  Naoto Horiguchi

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/08

CPC classification number: H01L29/0653 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/823425 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/41725 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6681 ,  H01L29/775

Abstract: A method of forming an internal spacer between nanowires, the method involving: providing a fin comprising a stack of layers of sacrificial material alternated with nanowire material, and selectively removing part of the sacrificial material, thereby forming a recess. The method also involves depositing dielectric material into the recess resulting in dielectric material within the recess and excess dielectric material outside the recess, where a crevice remains in the dielectric material in each recess, and removing the excess dielectric material using a first etchant. The method also involves enlarging the crevices to form a gap using a second etchant such that a remaining dielectric material still covers the sacrificial material and partly covers the nanowire material, and such that outer ends of the nanowire material are accessible; and growing electrode material on the outer ends such that the electrode material from neighboring outer ends merge, thereby covering the gap.

公开(公告)号：US20180174927A1

公开(公告)日：2018-06-21

申请号：US15819049

申请日：2017-11-21

Applicant: IMEC VZW

Inventor： Naoto Horiguchi ,  Andriy Hikavyy ,  Steven Demuynck

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/306 ,  H01L29/08 ,  H01L29/78 ,  H01L29/786 ,  H01L29/06 ,  H01L27/092

CPC classification number: H01L21/823871 ,  B82Y10/00 ,  H01L21/02603 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/413 ,  H01L29/417 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78618 ,  H01L29/78696 ,  H01L2029/7858

Abstract: An example embodiment relates to a method for making a contact to a source or drain region of a semiconductor device. The method may include providing the semiconductor device having at least one source or drain region, the source or drain region having an exposed area. The method may further include partially etching the source or drain region such that the exposed area is increased. The method may further include providing a contact covering at least the etched part of the source or drain region. The contact may contact the source or drain region on at least 3 sides of the source or drain region.

公开(公告)号：US11545357B2

公开(公告)日：2023-01-03

申请号：US17110980

申请日：2020-12-03

Applicant: IMEC VZW

Inventor： Andriy Hikavyy ,  Clement Porret

IPC: H01L21/02 ,  H01L29/16 ,  H01L29/78

Abstract: A method for forming a Ga-doped SiGe layer comprises depositing, in the presence of a C-containing Ga precursor, Ga-doped SiGe on a substrate, thereby forming a first portion of the Ga-doped SiGe layer. The method further comprises depositing, in the absence of the C-containing Ga precursor, SiGe on the first portion, thereby forming a second portion of the Ga-doped SiGe layer.

公开(公告)号：US20210175069A1

公开(公告)日：2021-06-10

申请号：US17110980

申请日：2020-12-03

Applicant: IMEC VZW

Inventor： Andriy Hikavyy ,  Clement Porret

IPC: H01L21/02 ,  H01L29/16

Abstract: A method for forming a Ga-doped SiGe layer comprises depositing, in the presence of a C-containing Ga precursor, Ga-doped SiGe on a substrate, thereby forming a first portion of the Ga-doped SiGe layer. The method further comprises depositing, in the absence of the C-containing Ga precursor, SiGe on the first portion, thereby forming a second portion of the Ga-doped SiGe layer.

公开(公告)号：US20140024204A1

公开(公告)日：2014-01-23

申请号：US13944592

申请日：2013-07-17

Applicant: IMEC

Inventor： Andriy Hikavyy ,  Benjamin Vincent ,  Roger Loo

IPC: H01L21/02

CPC classification number: H01L21/02636 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/2053

Abstract: Disclosed are methods for selective deposition of doped Group IV-Sn materials. In some embodiments, the method includes providing a patterned substrate comprising at least a first region and a second region, where the first region includes an exposed first semiconductor material and the second region includes an exposed insulator material, and performing at least two cycles of a grow-etch cyclic process. Each cycle includes depositing a doped Group IV-Tin (Sn) layer, where depositing the doped Group IV-Sn layer includes providing a Group IV precursor, a Sn precursor, and a dopant precursor, and using an etch gas to etch back the deposited doped Group IV-Sn layer.

Abstract translation: 公开了用于选择性沉积掺杂的IV-Sn族材料的方法。 在一些实施例中，该方法包括提供包括至少第一区域和第二区域的图案化衬底，其中第一区域包括暴露的第一半导体材料，并且第二区域包括暴露的绝缘体材料，并且执行至少两个循环 生长蚀刻循环过程。 每个循环包括沉积掺杂的IV族锡（Sn）层，其中沉积掺杂的IV-Sn层包括提供IV族前体，Sn前体和掺杂剂前体，并使用蚀刻气体来回蚀刻沉积 掺杂IV-Sn层。