公开(公告)号：US20200312726A1

公开(公告)日：2020-10-01

申请号：US16836653

申请日：2020-03-31

Applicant: IMEC vzw

Inventor： Anabela Veloso ,  Trong Huynh Bao ,  Julien Ryckaert ,  Raf Appeltans

IPC: H01L21/8234 ,  H01L27/088

Abstract: A method of fabricating a semiconductor device is disclosed. In one aspect, the method includes forming, in a vertical channel field-effect transistor (FET) device region, a vertical channel FET device including a first semiconductor structure including a lower source/drain portion, an upper source/drain portion, a first channel portion extending vertically and intermediate the source/drain portions and a gate structure extending along the channel portion and, in a horizontal channel FET device region, a horizontal channel FET device comprising a second semiconductor structure including a first source/drain portion, a second source/drain portion, a second channel portion extending horizontally and intermediate the source/drain portions, and a gate structure extending across the channel portion.

公开(公告)号：US10720363B2

公开(公告)日：2020-07-21

申请号：US15977381

申请日：2018-05-11

Applicant: IMEC VZW ,  Vrije Universiteit Brussel

Inventor： Julien Ryckaert ,  Naoto Horiguchi ,  Dan Mocuta ,  Trong Huynh Bao

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L21/285 ,  H01L21/306 ,  H01L29/78 ,  H01L21/762 ,  H01L23/528 ,  H01L27/11 ,  H01L27/092 ,  H01L29/06 ,  H01L29/45 ,  H01L21/308 ,  H01L29/66 ,  H01L29/786

Abstract: The disclosed technology generally relates to semiconductor fabrication and more particularly to forming vertical transistor devices. In an aspect, a method of forming a vertical transistor device includes forming, on a substrate, a fin comprising a stack including a first layer, a second layer formed above the first layer and a third layer formed above the second layer. The method additionally includes forming a gate layer serving as an etch mask above the third layer. The method further includes etching the second and third layers of the fin using the gate layer as the etch mask to form a pillar. First and third layers of the pillar define a source region and a drain region, respectively, of the vertical transistor device. A second layer of the pillar defines a channel region of the vertical transistor device. The gate layer comprises a gate electrode arranged on at least one sidewall of the second layer.

公开(公告)号：US10522552B2

公开(公告)日：2019-12-31

申请号：US15980604

申请日：2018-05-15

Applicant: IMEC VZW

Inventor： Julien Ryckaert ,  Naoto Horiguchi ,  Dan Mocuta ,  Trong Huynh Bao

IPC: H01L21/8234 ,  H01L27/11 ,  H01L27/088 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/786

Abstract: The disclosed technology generally relates semiconductor devices and more particularly to a vertical transistor device, and a method of fabricating the same. In one aspect, the method includes providing, on a substrate, a fin formed of a stack of a first layer, a second layer and a third layer, wherein the second layer is positioned above the first layer and the third layer is positioned above the second layer. The method additionally includes forming a dielectric on the sidewalls of the first and third layers of the fin selectively against a sidewall of the second layer, and the method additionally includes forming a gate contacting layer for contacting a sidewall of the second layer. The first and third layers define a source region and a drain region, respectively, of the vertical transistor device. The second layer defines a channel region of the vertical transistor device. The dielectric on the sidewalls of the first and third layers electrically isolates the source and drain regions from the gate contacting layer.

公开(公告)号：US10332588B2

公开(公告)日：2019-06-25

申请号：US15851531

申请日：2017-12-21

Applicant: IMEC VZW ,  Vrije Universiteit Brussel

Inventor： Trong Huynh Bao ,  Julien Ryckaert ,  Praveen Raghavan ,  Pieter Weckx

IPC: G11C11/412 ,  H01L27/11 ,  H01L29/423 ,  G11C11/408 ,  H01L29/08 ,  H01L27/06 ,  H01L29/06

Abstract: In an aspect of the disclosed technology, a SRAM device includes a first stack of transistors and a second stack of transistors arranged on a substrate. Each of the first and second stacks includes a pull-up transistor, a pull-down transistor and a pass transistor, where each of the transistors includes a horizontally extending channel. In each of the first and second stacks, the pull-up transistor and the pull-down transistor have a common gate electrode extending vertically therebetween, and the pass transistor has a gate electrode separated from the common gate electrode. A source/drain of each of the pull-up transistor and the pull-down transistor and a source/drain of the pass transistor included in one of the first stack and the second stack are electrically interconnected with the common gate electrode of the pull-up transistor and the pull-down transistor included in the other of the first stack and the second stack.

公开(公告)号：US11832525B2

公开(公告)日：2023-11-28

申请号：US17119010

申请日：2020-12-11

Applicant: IMEC vzw ,  Katholieke Universiteit Leuven

Inventor： Mohit Gupta ,  Trong Huynh Bao

IPC: H10N50/10 ,  G11C11/16 ,  H01F10/32 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10N50/10 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1673 ,  G11C11/1675 ,  H01F10/329 ,  H01F10/3286 ,  H10N50/80 ,  H10N50/85

Abstract: The material layer stack includes first and second magnetic tunnel junctions and a first top electrode formed on a top face of the stack. A shoulder is formed on a lateral face of the stack and divides the stack into a lower portion and an upper portion. A tunnel barrier of the first magnetic tunnel junction is comprised by the lower stack portion and a tunnel barrier of the second magnetic tunnel junction by the upper stack portion. A second top electrode is formed on the shoulder. Each magnetic tunnel junction is adapted to store a bit as a reconfigurable magnetoresistance of its magnetic electrodes. Preferably, a bottom face of the stack is connected to a conductor supporting current induced magnetic polarization switching for the first magnetic tunnel junction by spin-orbit torque. Magnetic polarization switching for the second magnetic tunnel junction is preferably achieved by spin-transfer torque.

公开(公告)号：US11227645B2

公开(公告)日：2022-01-18

申请号：US16705937

申请日：2019-12-06

Applicant: IMEC VZW ,  VRIJE UNIVERSITEIT BRUSSEL

Inventor： Sushil Sakhare ,  Manu Komalan Perumkunnil ,  Johan Swerts ,  Gouri Sankar Kar ,  Trong Huynh Bao

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: According to an example embodiment an MTJ unit is provided. The MTJ unit includes: a first MTJ comprising a first free layer, a first tunnel barrier layer and a first reference layer. The first MTJ is switchable between a parallel state and an anti-parallel state through spin-torque transfer (STT). The MTJ unit comprises a second MTJ arranged above the first MTJ and comprising, a second reference layer, a second tunnel barrier layer and a second free layer. The second MTJ is switchable between a parallel state and an anti-parallel state through STT. The MTJ unit comprises a pinning layer arranged between the first reference layer and the second reference layer and configured to fix a magnetization direction of the first reference layer and the second reference layer.

公开(公告)号：US11201093B2

公开(公告)日：2021-12-14

申请号：US16836653

申请日：2020-03-31

Applicant: IMEC vzw

Inventor： Anabela Veloso ,  Trong Huynh Bao ,  Julien Ryckaert ,  Raf Appeltans

IPC: H01L21/8234 ,  H01L27/088

Abstract: A method of fabricating a semiconductor device is disclosed. In one aspect, the method includes forming, in a vertical channel field-effect transistor (FET) device region, a vertical channel FET device including a first semiconductor structure including a lower source/drain portion, an upper source/drain portion, a first channel portion extending vertically and intermediate the source/drain portions and a gate structure extending along the channel portion and, in a horizontal channel FET device region, a horizontal channel FET device comprising a second semiconductor structure including a first source/drain portion, a second source/drain portion, a second channel portion extending horizontally and intermediate the source/drain portions, and a gate structure extending across the channel portion.

公开(公告)号：US11087837B2

公开(公告)日：2021-08-10

申请号：US16727653

申请日：2019-12-26

Applicant: IMEC VZW

Inventor： Trong Huynh Bao ,  Sushil Sakhare

IPC: G11C8/10 ,  G11C17/02 ,  G11C13/00 ,  G11C14/00

Abstract: A circuit cell for a memory device or a logic device comprises: (i) first and a second logic gates having respective output nodes; and (ii) first and second memory units, each comprising (a) first and second terminals and (b) a resistive memory element and a bipolar selector connected in series between the first and second terminals, wherein the first terminals of the first and second memory units are connected to the output nodes of the first and second logic gates, respectively, wherein the resistive memory elements are configured to be switchable between first and second resistance states, and wherein in response to a switching current and the bipolar selectors are configured to be conducting in response to an absolute value of a voltage difference across the bipolar selectors exceeding a threshold voltage of the bipolar selectors and non-conducting in response to the absolute value being lower than the threshold.

公开(公告)号：US20200185016A1

公开(公告)日：2020-06-11

申请号：US16705937

申请日：2019-12-06

Applicant: IMEC VZW ,  VRIJE UNIVERSITEIT BRUSSEL

Inventor： Sushil Sakhare ,  Manu Komalan Perumkunnil ,  Johan Swerts ,  Gouri Sankar Kar ,  Trong Huynh Bao

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: According to an example embodiment an MTJ unit is provided. The MTJ unit includes: a first MTJ comprising a first free layer, a first tunnel barrier layer and a first reference layer. The first MTJ is switchable between a parallel state and an anti-parallel state through spin-torque transfer (STT). The MTJ unit comprises a second MTJ arranged above the first MTJ and comprising, a second reference layer, a second tunnel barrier layer and a second free layer. The second MTJ is switchable between a parallel state and an anti-parallel state through STT. The MTJ unit comprises a pinning layer arranged between the first reference layer and the second reference layer and configured to fix a magnetization direction of the first reference layer and the second reference layer.

公开(公告)号：US10325647B2

公开(公告)日：2019-06-18

申请号：US15833802

申请日：2017-12-06

Applicant: IMEC VZW ,  VRIJE UNIVERSITEIT BRUSSEL ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

Inventor： Sushil Sakhare ,  Trong Huynh Bao ,  Manu Komalan Perumkunnil

IPC: G11C14/00 ,  G11C11/417 ,  G11C13/00 ,  G11C11/16 ,  G11C11/412 ,  G11C11/419

Abstract: A memory cell is disclosed, comprising a static random-access memory, SRAM, bit cell, a first resistive memory element and a second resistive memory element. The first resistive memory element is connected to a first storage node of the SRAM bit cell and a first intermediate node, and the second resistive memory element connected to a second storage node of the SRAM bit cell and a second intermediate node. Each one of the first intermediate node and the second intermediate node is configured to be supplied with a first supply voltage via a first transistor and a second supply voltage via a second transistor, wherein the first transistor and the second transistor are complementary transistors separately controllable by a first word line and a second word line, respectively. Methods for operating such a memory cell are also disclosed.