公开(公告)号：US20170257037A1

公开(公告)日：2017-09-07

申请号：US15446568

申请日：2017-03-01

Applicant: Infineon Technologies AG

Inventor： Juergen Kositza ,  Herbert Gietler ,  Harald Huber ,  Michael Lenz

IPC: H02M7/217 ,  H02M1/084 ,  H02M7/06

Abstract: A power semiconductor package includes a reference voltage terminal, a supply voltage terminal, a phase terminal, a first power transistor and a second power transistor. The first power transistor and the second power transistor are connected in series and form a low side switch and a high side switch of a half bridge circuit.

公开(公告)号：US09728480B2

公开(公告)日：2017-08-08

申请号：US14699704

申请日：2015-04-29

Applicant: Infineon Technologies AG

Inventor： Kurt Matoy ,  Hubert Maier ,  Christian Krenn ,  Elfriede Kraxner Wellenzohn ,  Helmut Schoenherr ,  Juergen Steinbrenner ,  Markus Kahn ,  Silvana Fister ,  Christoph Brunner ,  Herbert Gietler ,  Uwe Hoeckele

IPC: H01L21/3105 ,  H01L23/31 ,  H01L21/02 ,  H01L23/29

CPC classification number: H01L23/3171 ,  H01L21/0206 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/02334 ,  H01L21/0234 ,  H01L21/76801 ,  H01L23/291

Abstract: A passivation layer and a method of making a passivation layer are disclosed. In one embodiment the method for manufacturing a passivation layer includes depositing a first silicon based dielectric layer on a workpiece, the first silicon based dielectric layer comprising nitrogen, and depositing in-situ a second silicon based dielectric layer on the first silicon based dielectric layer, the second dielectric layer comprising oxygen.

公开(公告)号：US09589914B2

公开(公告)日：2017-03-07

申请号：US14555735

申请日：2014-11-28

Applicant: Infineon Technologies AG

Inventor： Herbert Gietler ,  Robert Pressl

IPC: H01L23/58 ,  H01L29/06 ,  G01R31/26 ,  H01L21/66

CPC classification number: H01L22/34 ,  G01N27/24 ,  G01R31/2601 ,  G01R31/2831 ,  H01L23/58 ,  H01L23/642 ,  H01L29/0649 ,  H01L29/0684 ,  H01L2924/0002 ,  H01L2924/00

Abstract: According to various embodiments, a semiconductor chip may include: a semiconductor body region including a first surface and a second surface opposite the first surface; a capacitive structure for detecting crack propagation into the semiconductor body region; wherein the capacitive structure may include a first electrode region at least partially surrounding the semiconductor body region and at least substantially extending from the first surface to the second surface; wherein the capacitive structure further may include a second electrode region disposed next to the first electrode region and an electrically insulating region extending between the first electrode region and the second electrode region.

Abstract translation: 根据各种实施例，半导体芯片可以包括：半导体主体区域，包括第一表面和与第一表面相对的第二表面; 用于检测裂纹传播到半导体本体区域中的电容结构; 其中所述电容结构可以包括至少部分地围绕所述半导体本体区域并且至少基本上从所述第一表面延伸到所述第二表面的第一电极区域; 其中所述电容结构还可包括邻近所述第一电极区设置的第二电极区和在所述第一电极区和所述第二电极区之间延伸的电绝缘区。

公开(公告)号：US08766444B2

公开(公告)日：2014-07-01

申请号：US13739389

申请日：2013-01-11

Applicant: Infineon Technologies AG

Inventor： Herbert Gietler ,  Gerhard Zojer ,  Benjamin Finke

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/5384 ,  H01L23/4824 ,  H01L23/522 ,  H01L24/06 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00

Abstract: An integrated circuit as described herein includes an upper interconnect level including a continuous upper interconnect area, the continuous upper interconnect area including a plurality of upper contact openings. The integrated circuit further includes a lower interconnect level including a continuous lower interconnect area, the continuous lower interconnect area including a plurality of lower contact openings. First contacts extend through the lower contact openings to the upper interconnect area and second contact openings extend through the upper contact openings to the lower interconnect area.

Abstract translation: 如本文所述的集成电路包括上互连电平，其包括连续的上互连区域，所述连续上互连区域包括多个上接触开口。 集成电路还包括下连接级，其包括连续的下互连区域，连续的下互连区域包括多个下接触开口。 第一触点延伸穿过下接触开口到上互连区域，第二接触开口延伸通过上接触开口到下互连区域。

公开(公告)号：US10522432B2

公开(公告)日：2019-12-31

申请号：US15413442

申请日：2017-01-24

Applicant: Infineon Technologies AG

Inventor： Herbert Gietler ,  Robert Pressl

IPC: H01L23/58 ,  H01L21/66 ,  H01L29/06 ,  G01R31/26 ,  G01N27/24 ,  G01R31/28 ,  H01L23/64 ,  H01L21/78

Abstract: According to various embodiments, a semiconductor chip may include: a semiconductor body region including a first surface and a second surface opposite the first surface; a capacitive structure for detecting crack propagation into the semiconductor body region; wherein the capacitive structure may include a first electrode region at least partially surrounding the semiconductor body region and at least substantially extending from the first surface to the second surface; wherein the capacitive structure further may include a second electrode region disposed next to the first electrode region and an electrically insulating region extending between the first electrode region and the second electrode region.

公开(公告)号：US09997608B2

公开(公告)日：2018-06-12

申请号：US15404285

申请日：2017-01-12

Applicant: Infineon Technologies AG

Inventor： Karoline Koepp ,  Herbert Gietler

IPC: H01L29/423 ,  H01L29/40 ,  H01L29/417 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/4238 ,  H01L29/0696 ,  H01L29/40 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/41741 ,  H01L29/7813

Abstract: Disclosed is a transistor device. The transistor device includes a plurality of device cells each having an active device region integrated in a semiconductor body and electrically connected to a contact layer. The contact layer includes a plurality of layer sections separated from each other by a separation layer. A resistivity of the separation layer is at least 100 times the resistivity of the layer sections.

公开(公告)号：US20170200795A1

公开(公告)日：2017-07-13

申请号：US15404285

申请日：2017-01-12

Applicant: Infineon Technologies AG

Inventor： Karoline Koepp ,  Herbert Gietler

IPC: H01L29/417 ,  H01L29/40 ,  H01L29/423

CPC classification number: H01L29/4238 ,  H01L29/0696 ,  H01L29/40 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/41741 ,  H01L29/7813

Abstract: Disclosed is a transistor device. The transistor device includes a plurality of device cells each having an active device region integrated in a semiconductor body and electrically connected to a contact layer. The contact layer includes a plurality of layer sections separated from each other by a separation layer. A resistivity of the separation layer is at least 100 times the resistivity of the layer sections.

公开(公告)号：US20130127066A1

公开(公告)日：2013-05-23

申请号：US13739389

申请日：2013-01-11

Applicant: Infineon Technologies AG

Inventor： Herbert Gietler ,  Gerhard Zojer ,  Benjamin Finke

IPC: H01L23/538

CPC classification number: H01L23/5384 ,  H01L23/4824 ,  H01L23/522 ,  H01L24/06 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/00

Abstract: An integrated circuit as described herein includes an upper interconnect level including a continuous upper interconnect area, the continuous upper interconnect area including a plurality of upper contact openings. The integrated circuit further includes a lower interconnect level including a continuous lower interconnect area, the continuous lower interconnect area including a plurality of lower contact openings. First contacts extend through the lower contact openings to the upper interconnect area and second contact openings extend through the upper contact openings to the lower interconnect area.

Abstract translation: 如本文所述的集成电路包括包括连续上部互连区域的上部互连级别，连续的上部互连区域包括多个上部接触开口。 集成电路还包括下连接级，其包括连续的下互连区域，连续的下互连区域包括多个下接触开口。 第一触点延伸穿过下接触开口到上互连区域，第二接触开口延伸通过上接触开口到下互连区域。