公开(公告)号：US20150348921A1

公开(公告)日：2015-12-03

申请号：US14290448

申请日：2014-05-29

Applicant: Infineon Technologies AG

Inventor： Paul Ganitzer ,  Rudolf Zelsacher

IPC: H01L23/00 ,  H01L21/82

CPC classification number: H01L24/03 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/82 ,  H01L24/05 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2224/03002 ,  H01L2224/0312 ,  H01L2224/0345 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/0348 ,  H01L2224/0361 ,  H01L2224/03614 ,  H01L2224/0362 ,  H01L2224/05016 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05082 ,  H01L2224/05084 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05562 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/05672 ,  H01L2224/80203 ,  H01L2224/80825 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2224/05624

Abstract: In an embodiment of the present invention, a method of forming a semiconductor device includes providing a semiconductor substrate including a first chip region and a second chip region. A first contact pad is formed over the first chip region and a second contact pad is formed over the second chip region. The first and the second contact pads are at least as thick as the semiconductor substrate. The method further includes dicing through the semiconductor substrate between the first and the second contact pads. The dicing is performed from a side of the semiconductor substrate including the first contact pad and the second contact pad. A conductive liner is formed over the first and the second contact pads and sidewalls of the semiconductor substrate exposed by the dicing.

Abstract translation: 在本发明的实施例中，形成半导体器件的方法包括提供包括第一芯片区域和第二芯片区域的半导体衬底。 在第一芯片区域上形成第一接触焊盘，并且在第二芯片区域上形成第二接触焊盘。 第一和第二接触焊盘至少与半导体衬底一样厚。 该方法还包括在第一和第二接触焊盘之间切割通过半导体衬底。 从包括第一接触焊盘和第二接触焊盘的半导体衬底的一侧进行切割。 导电衬垫形成在半导体衬底的第一接触焊盘和第二接触焊盘和通过切割而暴露的侧壁之间。

公开(公告)号：US11848237B2

公开(公告)日：2023-12-19

申请号：US17678619

申请日：2022-02-23

Applicant: Infineon Technologies AG

Inventor： Paul Ganitzer ,  Carsten von Koblinski ,  Thomas Feil ,  Gerald Lackner ,  Jochen Mueller ,  Martin Poelzl ,  Tobias Polster

IPC: H01L23/48 ,  H01L21/8234 ,  H01L21/56 ,  H01L21/78 ,  H01L23/495 ,  H01L21/762 ,  H01L21/768 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L21/8234 ,  H01L21/561 ,  H01L21/762 ,  H01L21/76873 ,  H01L21/78 ,  H01L23/481 ,  H01L23/49562 ,  H01L25/0655 ,  H01L23/3114 ,  H01L23/3135 ,  H01L2224/06181 ,  H01L2224/16245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73257 ,  H01L2924/181 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/48465 ,  H01L2224/48247 ,  H01L2924/00

Abstract: An electronic component includes a semiconductor device including a semiconductor die including a first surface, the first surface including a first metallization structure and edge regions surrounding the first metallization structure, a second surface opposing the first surface and including a second metallization structure, and side faces extending between the first surface and the second surface, wherein the edge regions of the first surface and portions of the side faces are covered by a first polymer layer, wherein the electronic component further includes a plurality of leads and a plastic housing composition, wherein the first metallization structure is coupled to a first lead and the second metallization structure is coupled to a second lead of the plurality of leads.

公开(公告)号：US10672664B2

公开(公告)日：2020-06-02

申请号：US16081236

申请日：2017-02-27

Applicant: Infineon Technologies AG

Inventor： Paul Ganitzer ,  Carsten von Koblinski ,  Thomas Feil ,  Gerald Lackner ,  Jochen Mueller ,  Martin Poelzl ,  Tobias Polster

IPC: H01L21/78 ,  H01L21/8234 ,  H01L21/56 ,  H01L23/495 ,  H01L21/762 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065 ,  H01L23/31

Abstract: In an embodiment, a method includes forming at least one trench in non-device regions of a first surface of a semiconductor wafer, the non-device regions being arranged between component positions, the component positions including device regions and a first metallization structure, applying a first polymer layer to the first surface of a semiconductor wafer such that the trenches and edge regions of the component positions are covered with the first polymer layer and such that at least a portion of the first metallization structure is uncovered by the first polymer layer, removing portions of a second surface of the semiconductor wafer, the second surface opposing the first surface, revealing portions of the first polymer layer in the non-device regions and producing a worked second surface and inserting a separation line through the first polymer layer in the non-device regions to form a plurality of separate semiconductor dies.

公开(公告)号：US11552016B2

公开(公告)日：2023-01-10

申请号：US17170359

申请日：2021-02-08

Applicant: Infineon Technologies AG

Inventor： Paul Ganitzer ,  Martin Poelzl

IPC: H01L23/528 ,  H01L23/532 ,  H01L23/535 ,  H01L21/78 ,  H01L23/495 ,  H01L21/48 ,  H01L29/78 ,  H01L23/482 ,  H01L21/683 ,  H01L21/3213 ,  H01L23/00 ,  H01L23/31 ,  H01L29/40

Abstract: A semiconductor device includes a semiconductor layer with a thickness of at most 50 μm. A first metallization structure is disposed on a first surface of the semiconductor layer. The first metallization structure includes a first copper region with a first thickness. A second metallization structure is disposed on a second surface of the semiconductor layer opposite to the first surface. The second metallization structure includes a second copper region with a second thickness.

公开(公告)号：US20220181211A1

公开(公告)日：2022-06-09

申请号：US17678619

申请日：2022-02-23

Applicant: Infineon Technologies AG

Inventor： Paul Ganitzer ,  Carsten von Koblinski ,  Thomas Feil ,  Gerald Lackner ,  Jochen Mueller ,  Martin Poelzl ,  Tobias Polster

IPC: H01L21/8234 ,  H01L21/56 ,  H01L21/78 ,  H01L23/495 ,  H01L21/762 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065

Abstract: An electronic component includes a semiconductor device including a semiconductor die including a first surface, the first surface including a first metallization structure and edge regions surrounding the first metallization structure, a second surface opposing the first surface and including a second metallization structure, and side faces extending between the first surface and the second surface, wherein the edge regions of the first surface and portions of the side faces are covered by a first polymer layer, wherein the electronic component further includes a plurality of leads and a plastic housing composition, wherein the first metallization structure is coupled to a first lead and the second metallization structure is coupled to a second lead of the plurality of leads.

公开(公告)号：US20190259874A1

公开(公告)日：2019-08-22

申请号：US16398277

申请日：2019-04-30

Applicant: Infineon Technologies AG

Inventor： Paul Ganitzer ,  Arno Zechmann ,  Michael Jacob

IPC: H01L29/78 ,  H01L23/31 ,  H01L29/10 ,  H01L29/417 ,  H01L29/45 ,  H01L29/66 ,  H01L23/485 ,  H01L21/283

Abstract: In various embodiments a semiconductor device is provided, including a semiconductor body including a drift region and a gate electrode arranged adjacent to the drift region; and a contact structure provided over the drift region of the semiconductor body and having a first metal layer, an adhesion layer over the first metal layer and a second metal layer over the adhesion layer.

公开(公告)号：US20190088550A1

公开(公告)日：2019-03-21

申请号：US16081236

申请日：2017-02-27

Applicant: Infineon Technologies AG

Inventor： Paul Ganitzer ,  Carsten von Koblinski ,  Thomas Feil ,  Gerald Lackner ,  Jochen Mueller ,  Martin Poelzl ,  Tobias Polster

IPC: H01L21/8234 ,  H01L21/768 ,  H01L21/762 ,  H01L21/56 ,  H01L23/48 ,  H01L25/065

Abstract: In an embodiment, a method includes forming at least one trench in non-device regions of a first surface of a semiconductor wafer, the non-device regions being arranged between component positions, the component positions including device regions and a first metallization structure, applying a first polymer layer to the first surface of a semiconductor wafer such that the trenches and edge regions of the component positions are covered with the first polymer layer and such that at least a portion of the first metallization structure is uncovered by the first polymer layer, removing portions of a second surface of the semiconductor wafer, the second surface opposing the first surface, revealing portions of the first polymer layer in the non-device regions and producing a worked second surface and inserting a separation line through the first polymer layer in the non-device regions to form a plurality of separate semiconductor dies.

公开(公告)号：US20180138120A1

公开(公告)日：2018-05-17

申请号：US15804396

申请日：2017-11-06

Applicant: Infineon Technologies AG

Inventor： Paul Ganitzer ,  Martin Poelzl

IPC: H01L23/528 ,  H01L23/532 ,  H01L23/535 ,  H01L29/78 ,  H01L23/495 ,  H01L21/48 ,  H01L21/78

CPC classification number: H01L23/528 ,  H01L21/32139 ,  H01L21/4857 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/482 ,  H01L23/49527 ,  H01L23/49551 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/53238 ,  H01L23/535 ,  H01L23/562 ,  H01L29/404 ,  H01L29/407 ,  H01L29/7813 ,  H01L2224/48091 ,  H01L2924/00014

Abstract: A semiconductor device includes a semiconductor layer with a thickness of at most 50 μm. A first metallization structure is disposed on a first surface of the semiconductor layer. The first metallization structure includes a first copper region with a first thickness. A second metallization structure is disposed on a second surface of the semiconductor layer opposite to the first surface. The second metallization structure includes a second copper region with a second thickness. The total thickness, which is the sum of the first thickness and the second thickness, deviates from the thickness of the semiconductor layer by not more than 20% and a difference between the first thickness and the second thickness is not more than 20% of the total thickness.

公开(公告)号：US20160307858A1

公开(公告)日：2016-10-20

申请号：US15195434

申请日：2016-06-28

Applicant: Infineon Technologies AG

Inventor： Paul Ganitzer ,  Rudolf Zelsacher

IPC: H01L23/00 ,  H01L21/82

CPC classification number: H01L24/03 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/82 ,  H01L24/05 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2224/03002 ,  H01L2224/0312 ,  H01L2224/0345 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/0348 ,  H01L2224/0361 ,  H01L2224/03614 ,  H01L2224/0362 ,  H01L2224/05016 ,  H01L2224/05022 ,  H01L2224/05023 ,  H01L2224/05082 ,  H01L2224/05084 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05562 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05664 ,  H01L2224/05672 ,  H01L2224/80203 ,  H01L2224/80825 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2224/03 ,  H01L2924/00014 ,  H01L2224/05624

Abstract: In an embodiment of the present invention, a method of forming a semiconductor device includes providing a semiconductor substrate including a first chip region and a second chip region. A first contact pad is formed over the first chip region and a second contact pad is formed over the second chip region. The first and the second contact pads are at least as thick as the semiconductor substrate. The method further includes dicing through the semiconductor substrate between the first and the second contact pads. The dicing is performed from a side of the semiconductor substrate including the first contact pad and the second contact pad. A conductive liner is formed over the first and the second contact pads and sidewalls of the semiconductor substrate exposed by the dicing.

Abstract translation: 在本发明的实施例中，形成半导体器件的方法包括提供包括第一芯片区域和第二芯片区域的半导体衬底。 在第一芯片区域上形成第一接触焊盘，并且在第二芯片区域上形成第二接触焊盘。 第一和第二接触焊盘至少与半导体衬底一样厚。 该方法还包括在第一和第二接触焊盘之间切割通过半导体衬底。 从包括第一接触焊盘和第二接触焊盘的半导体衬底的一侧进行切割。 导电衬垫形成在半导体衬底的第一接触焊盘和第二接触焊盘和通过切割而暴露的侧壁之间。

公开(公告)号：US20150221764A1

公开(公告)日：2015-08-06

申请号：US14171839

申请日：2014-02-04

Applicant: Infineon Technologies AG

Inventor： Paul Ganitzer ,  Arno Zechmann ,  Michael Jacob

IPC: H01L29/78 ,  H01L23/31 ,  H01L21/283 ,  H01L29/66 ,  H01L29/10 ,  H01L29/45

CPC classification number: H01L29/7813 ,  H01L21/283 ,  H01L23/3157 ,  H01L23/3171 ,  H01L23/485 ,  H01L23/53238 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/45 ,  H01L29/66666 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In various embodiments a semiconductor device is provided, including a semiconductor body including a drift region and a gate electrode arranged adjacent to the drift region; and a contact structure provided over the drift region of the semiconductor body and having a first metal layer, an adhesion layer over the first metal layer and a second metal layer over the adhesion layer.

Abstract translation: 在各种实施例中，提供了一种半导体器件，包括包括漂移区的半导体本体和与漂移区相邻布置的栅极; 以及设置在所述半导体主体的漂移区上方并且具有第一金属层，在所述第一金属层上方的粘合层和所述粘附层上的第二金属层的接触结构。