公开(公告)号：US20160218033A1

公开(公告)日：2016-07-28

申请号：US14607708

申请日：2015-01-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Ravi Keshav Joshi ,  Juergen Steinbrenner ,  Christian Fachmann ,  Petra Fischer ,  Roman Roth

IPC: H01L21/768 ,  H01L21/3213 ,  H01L23/532 ,  H01L21/285

CPC classification number: H01L23/53238 ,  H01L21/32134 ,  H01L21/32139 ,  H01L21/76885 ,  H01L24/00 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a metallization layer over a semiconductor substrate includes depositing a blanket layer of a diffusion barrier liner over an inter level dielectric layer, and depositing a blanket layer of an intermediate layer over the diffusion barrier liner. A blanket layer of a power metal layer including copper is deposited over the intermediate layer. The intermediate layer includes a solid solution of a majority element and copper. The intermediate layer has a different etch selectivity from the power metal layer. After depositing the power metal layer, structuring the power metal layer, the intermediate layer, and the diffusion barrier liner.

Abstract translation: 在半导体衬底上形成金属化层的方法包括在层间电介质层上沉积扩散阻挡衬垫的覆盖层，以及在扩散阻挡衬里上沉积中间层的覆盖层。 包含铜的功率金属层的覆盖层沉积在中间层上。 中间层包括多数元素和铜的固溶体。 中间层具有与功率金属层不同的蚀刻选择性。 在沉积功率金属层之后，构建功率金属层，中间层和扩散阻挡衬里。

公开(公告)号：US11842938B2

公开(公告)日：2023-12-12

申请号：US17538162

申请日：2021-11-30

Applicant: Infineon Technologies AG

Inventor： Jens Peter Konrath ,  Wolfgang Bergner ,  Romain Esteve ,  Richard Gaisberger ,  Florian Grasse ,  Jochen Hilsenbeck ,  Ravi Keshav Joshi ,  Stefan Kramp ,  Stefan Krivec ,  Grzegorz Lupina ,  Hiroshi Narahashi ,  Andreas Voerckel ,  Stefan Woehlert

IPC: H01L23/31 ,  H01L23/29 ,  H01L21/56 ,  H01L29/16 ,  H01L29/861 ,  H01L29/78 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/3192 ,  H01L21/56 ,  H01L21/76841 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3171 ,  H01L23/53223 ,  H01L29/1608 ,  H01L29/7811 ,  H01L29/8611

Abstract: A semiconductor device includes a contact metallization layer that includes aluminum and is arranged on a semiconductor substrate, an inorganic passivation structure arranged on the semiconductor substrate, an organic passivation layer comprising a first part that is arranged on the contact metallization layer, and a second part that is arranged on the inorganic passivation structure, a first layer structure including a first part that is in contact with the contact metallization layer, a second part that is contact with the inorganic passivation structure, and a third part that is disposed on the semiconductor substrate laterally between the inorganic passivation structure and the organic passivation layer.

公开(公告)号：US11367683B2

公开(公告)日：2022-06-21

申请号：US16453222

申请日：2019-06-26

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Ravi Keshav Joshi ,  Ralf Siemieniec ,  Thomas Basler ,  Martin Gruber ,  Jochen Hilsenbeck ,  Dethard Peters ,  Roland Rupp ,  Wolfgang Scholz

IPC: H01L23/532 ,  H01L29/16 ,  H01L21/768 ,  H01L23/00 ,  H01L29/45

Abstract: A silicon carbide device includes a silicon carbide substrate, a contact layer including nickel, silicon and aluminum, a barrier layer structure including titanium and tungsten, and a metallization layer including copper. The contact layer is located on the silicon carbide substrate. The contact layer is located between the silicon carbide substrate and at least a part of the barrier layer structure. The barrier layer structure is located between the silicon carbide substrate and the metallization layer.

公开(公告)号：US20220093483A1

公开(公告)日：2022-03-24

申请号：US17538162

申请日：2021-11-30

Applicant: Infineon Technologies AG

Inventor： Jens Peter Konrath ,  Wolfgang Bergner ,  Romain Esteve ,  Richard Gaisberger ,  Florian Grasse ,  Jochen Hilsenbeck ,  Ravi Keshav Joshi ,  Stefan Kramp ,  Stefan Krivec ,  Grzegorz Lupina ,  Hiroshi Narahashi ,  Andreas Voerckel ,  Stefan Woehlert

IPC: H01L23/31 ,  H01L23/29 ,  H01L21/56 ,  H01L29/16 ,  H01L29/861 ,  H01L29/78 ,  H01L21/768 ,  H01L23/532

Abstract: A semiconductor device includes a contact metallization layer that includes aluminum and is arranged on a semiconductor substrate, an inorganic passivation structure arranged on the semiconductor substrate, an organic passivation layer comprising a first part that is arranged on the contact metallization layer, and a second part that is arranged on the inorganic passivation structure, a first layer structure including a first part that is in contact with the contact metallization layer, a second part that is contact with the inorganic passivation structure, and a third part that is disposed on the semiconductor substrate laterally between the inorganic passivation structure and the organic passivation layer.

公开(公告)号：US10580878B1

公开(公告)日：2020-03-03

申请号：US16105742

申请日：2018-08-20

Applicant: Infineon Technologies AG

Inventor： Ravi Keshav Joshi ,  Rudolf Elpelt ,  Romain Esteve

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L29/16

Abstract: A SiC device with a doped buried region is provided. The doped buried region may be formed by: forming a first trench which extends into a first side of a SiC epitaxial layer of a first conductivity type, the first trench terminating at a first depth in the SiC epitaxial layer; at least partly filling the first trench with an epitaxial material of a second conductivity type opposite the first conductivity type; forming a second trench which extends into the first side of the SiC epitaxial layer so that the second trench overlaps the first trench, the second trench terminates at a second depth in the SiC epitaxial layer which is less than the first depth, and the epitaxial material in the first trench laterally extends below a bottom of the second trench; and forming a gate electrode in the second trench and electrically insulated from the SiC epitaxial layer.

公开(公告)号：US20200058760A1

公开(公告)日：2020-02-20

申请号：US16105742

申请日：2018-08-20

Applicant: Infineon Technologies AG

Inventor： Ravi Keshav Joshi ,  Rudolf Elpelt ,  Romain Esteve

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/16 ,  H01L29/78 ,  H01L29/10

Abstract: A SiC device with a doped buried region is provided. The doped buried region may be formed by: forming a first trench which extends into a first side of a SiC epitaxial layer of a first conductivity type, the first trench terminating at a first depth in the SiC epitaxial layer; at least partly filling the first trench with an epitaxial material of a second conductivity type opposite the first conductivity type; forming a second trench which extends into the first side of the SiC epitaxial layer so that the second trench overlaps the first trench, the second trench terminates at a second depth in the SiC epitaxial layer which is less than the first depth, and the epitaxial material in the first trench laterally extends below a bottom of the second trench; and forming a gate electrode in the second trench and electrically insulated from the SiC epitaxial layer.

公开(公告)号：US20190355819A1

公开(公告)日：2019-11-21

申请号：US16412131

申请日：2019-05-14

Applicant: Infineon Technologies AG

Inventor： Ralf Siemieniec ,  Thomas Aichinger ,  Romain Esteve ,  Ravi Keshav Joshi ,  Shiqin Niu

IPC: H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423

Abstract: A semiconductor device includes a gate electrode and a gate dielectric. The gate electrode extends from a first surface of a silicon carbide body into the silicon carbide body. The gate dielectric is between the gate electrode and the silicon carbide body. The gate electrode includes a metal structure and a semiconductor layer between the metal structure and the gate dielectric.

公开(公告)号：US10121859B2

公开(公告)日：2018-11-06

申请号：US15457833

申请日：2017-03-13

Applicant: Infineon Technologies AG

Inventor： Ravi Keshav Joshi ,  Johannes Baumgartl ,  Oliver Blank ,  Oliver Hellmund ,  Martin Poelzl

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L21/78 ,  H01L21/68 ,  H01L21/683 ,  B81B7/00 ,  B81C1/00 ,  H01L29/40 ,  H01L29/78

Abstract: First reinforcement stripes are formed on a process surface of a base substrate. A first epitaxial layer covering the first reinforcement stripes is formed on the first process surface. Second reinforcement stripes are formed on the first epitaxial layer. A second epitaxial layer covering the second reinforcement stripes is formed on exposed portions of the first epitaxial layer. Semiconducting portions of transistor cells are formed in or portions of micro electromechanical structures are formed from the second epitaxial layer.

公开(公告)号：US20170271268A1

公开(公告)日：2017-09-21

申请号：US15458366

申请日：2017-03-14

Applicant: Infineon Technologies AG

Inventor： Frank Hille ,  Ravi Keshav Joshi ,  Michael Fugger ,  Oliver Humbel ,  Thomas Laska ,  Matthias Mueller ,  Roman Roth ,  Carsten Schaeffer ,  Hans-Joachim Schulze ,  Holger Schulze ,  Juergen Steinbrenner ,  Frank Umbach

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/53209 ,  H01L21/76846 ,  H01L21/76861 ,  H01L21/76898 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238

Abstract: According to an embodiment of a semiconductor device, the semiconductor devices includes a metal structure electrically connected to a semiconductor body and a metal adhesion and barrier structure between the metal structure and the semiconductor body. The metal adhesion and barrier structure includes a first layer having titanium and tungsten, and a second layer having titanium, tungsten, and nitrogen on the first layer having titanium and tungsten.

公开(公告)号：US20150280287A1

公开(公告)日：2015-10-01

申请号：US14230056

申请日：2014-03-31

Applicant: Infineon Technologies AG

Inventor： Ravi Keshav Joshi ,  Alexander Breymesser ,  Bernhard Goller ,  Kamil Karlovsky ,  Francisco Javier Santos Rodriguez ,  Peter Zorn

IPC: H01M10/42 ,  H01M2/02

Abstract: A battery includes a first substrate having a first main surface, a second substrate made of a conducting material or semiconductor material, and a carrier of an insulating material. The carrier has a first and a second main surfaces, the second substrate being attached to the first main surface of the carrier. An opening is formed in the second main surface of the carrier to uncover a portion of a second main surface of the second substrate. The second main surface of the carrier is attached to the first substrate, thereby forming a cavity. The battery further includes an electrolyte disposed in the cavity.

Abstract translation: 电池包括具有第一主表面的第一基底，由导电材料或半导体材料制成的第二基底和绝缘材料的载体。 载体具有第一和第二主表面，第二基底附接到载体的第一主表面。 在载体的第二主表面上形成开口以露出第二基板的第二主表面的一部分。 载体的第二主表面附接到第一基板，从而形成空腔。 电池还包括设置在空腔中的电解质。