中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

36 records (took 0.014 seconds)

    Coreless organic packages with embedded die and magnetic inductor structures
    11.
    发明授权
    Coreless organic packages with embedded die and magnetic inductor structures 有权

    公开(公告)号：US10700021B2

    公开(公告)日：2020-06-30

    申请号：US16119923

    申请日：2018-08-31

    Applicant: Intel Corporation

    Inventor： Andrew J. Brown ,  Rahul Jain ,  Prithwish Chatterjee ,  Lauren A. Link ,  Sai Vadlamani

    IPC: H01L23/00 ,  H01L23/64 ,  H01L23/538 ,  H01L21/48 ,  H01L21/683 ,  H01L21/78

    Abstract: A coreless semiconductor package comprises a plurality of horizontal layers of dielectric material. A magnetic inductor is situated at least partly in a first group of the plurality of layers. A plated laser stop is formed to protect the magnetic inductor against subsequent acidic processes. An EMIB is situated above the magnetic inductor within a second group of the plurality of layers. Vias and interconnections are configured within the horizontal layers to connect a die of the EMIB to other circuitry. A first level interconnect is formed on the top side of the package to connect to the interconnections. BGA pockets and BGA pads are formed on the bottom side of the package. In a second embodiment a polymer film is used as additional protection against subsequent acidic processes. The magnetic inductor comprises a plurality of copper traces encapsulated in magnetic material.

    CORELESS ORGANIC PACKAGES WITH EMBEDDED DIE AND MAGNETIC INDUCTOR STRUCTURES
    15.
    发明申请
    CORELESS ORGANIC PACKAGES WITH EMBEDDED DIE AND MAGNETIC INDUCTOR STRUCTURES 有权

    公开(公告)号：US20220068847A1

    公开(公告)日：2022-03-03

    申请号：US17524375

    申请日：2021-11-11

    Applicant: Intel Corporation

    Inventor： Andrew J. Brown ,  Rahul Jain ,  Prithwish Chatterjee ,  Lauren A. Link ,  Sai Vadlamani

    IPC: H01L23/64 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/683 ,  H01L21/78

    Abstract: A coreless semiconductor package comprises a plurality of horizontal layers of dielectric material. A magnetic inductor is situated at least partly in a first group of the plurality of layers. A plated laser stop is formed to protect the magnetic inductor against subsequent acidic processes. An EMIB is situated above the magnetic inductor within a second group of the plurality of layers. Vias and interconnections are configured within the horizontal layers to connect a die of the EMIB to other circuitry. A first level interconnect is formed on the top side of the package to connect to the interconnections. BGA pockets and BGA pads are formed on the bottom side of the package. In a second embodiment a polymer film is used as additional protection against subsequent acidic processes. The magnetic inductor comprises a plurality of copper traces encapsulated in magnetic material.

    PACKAGE SUBSTRATE WITH REDUCED INTERCONNECT STRESS
    17.
    发明申请
    PACKAGE SUBSTRATE WITH REDUCED INTERCONNECT STRESS 有权

    公开(公告)号：US20210050306A1

    公开(公告)日：2021-02-18

    申请号：US16541734

    申请日：2019-08-15

    Applicant: INTEL CORPORATION

    Inventor： Lauren A. Link ,  Andrew J. Brown ,  Sheng C. Li ,  Sandeep B. Sane

    IPC: H01L23/00 ,  H01L23/498 ,  H01L23/14 ,  H01L23/15

    Abstract: Techniques for mounting a semiconductor chip in a circuit board assembly includes using different buildup materials on opposite sides of a core to optimize stress in the first level interconnect structure (between the chip and core) and/or the second level interconnect structure (between the core and circuit board). The core can be, for example, ceramic, glass, or glass cloth-reinforced epoxy. In one example, the first side of the core has one or more layers of conductive material within a first buildup structure comprising a first buildup material. The second side of the substrate has one or more layers of conductive material within a second buildup structure comprising a second buildup material different from the first buildup material. In another example, an outermost layer of the second buildup structure is a ductile material that functions to decouple stress in the interconnect between the substrate and a circuit board.

    Sandwich-molded cores for high-inductance architectures
    19.
    发明授权
    Sandwich-molded cores for high-inductance architectures 有权

    公开(公告)号：US11622448B2

    公开(公告)日：2023-04-04

    申请号：US16505403

    申请日：2019-07-08

    Applicant: Intel Corporation

    Inventor： Brandon C. Marin ,  Tarek Ibrahim ,  Srinivas Pietambaram ,  Andrew J. Brown ,  Gang Duan ,  Jeremy Ecton ,  Sheng C. Li

    IPC: H05K1/11 ,  H05K1/16 ,  H01L23/00 ,  H01F27/40 ,  H05K3/40 ,  H05K3/28

    Abstract: Embodiments include package substrates and method of forming the package substrates. A package substrate includes a first encapsulation layer over a substrate, and a second encapsulation layer below the substrate. The package substrate also includes a first interconnect and a second interconnect vertically in the first encapsulation layer, the second encapsulation layer, and the substrate. The first interconnect includes a first plated-through-hole (PTH) core, a first via, and a second via, and the second interconnect includes a second PTH core, a third via, and a fourth via. The package substrate further includes a magnetic portion that vertically surrounds the first interconnect. The first PTH core has a top surface directly coupled to the first via, and a bottom surface directly coupled to the second via. The second PTH core has a top surface directly coupled to the third via, and a bottom surface directly coupled to the fourth via.

Patent Agency Ranking