公开(公告)号：US10338974B2

公开(公告)日：2019-07-02

申请号：US14126875

申请日：2013-11-06

Applicant: Intel Corporation

Inventor： Bahaa Fahim ,  Yen-Cheng Liu ,  Jeffrey D. Chamberlain

IPC: G06F9/46 ,  G06F9/52 ,  G06F9/48

Abstract: A starvation mode is entered and a particular dependency of a first request in a retry queue is identified. The particular dependency is determined to be acquired and the first request is retried based on acquisition of the particular dependency.

公开(公告)号：US12189550B2

公开(公告)日：2025-01-07

申请号：US18347236

申请日：2023-07-05

Applicant: Intel Corporation

Inventor： Robert J. Safranek ,  Robert G. Blankenship ,  Venkatraman Iyer ,  Jeff Willey ,  Robert Beers ,  Darren S. Jue ,  Arvind A. Kumar ,  Debendra Das Sharma ,  Jeffrey C. Swanson ,  Bahaa Fahim ,  Vedaraman Geetha ,  Aaron T. Spink ,  Fulvio Spagna ,  Rahul R. Shah ,  Sitaraman V. Iyer ,  William Harry Nale ,  Abhishek Das ,  Simon P. Johnson ,  Yuvraj S. Dhillon ,  Yen-Cheng Liu ,  Raj K. Ramanujan ,  Robert A. Maddox ,  Herbert H. Hum ,  Ashish Gupta

IPC: G06F13/22 ,  G06F1/3287 ,  G06F8/71 ,  G06F8/77 ,  G06F9/30 ,  G06F9/445 ,  G06F9/46 ,  G06F11/10 ,  G06F12/0806 ,  G06F12/0808 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0831 ,  G06F13/40 ,  G06F13/42 ,  H04L9/06 ,  H04L49/15 ,  G06F8/73 ,  H04L12/46 ,  H04L45/74

Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

公开(公告)号：US11669454B2

公开(公告)日：2023-06-06

申请号：US16405691

申请日：2019-05-07

Applicant: Intel Corporation

Inventor： Vedaraman Geetha ,  Jeffrey Baxter ,  Sai Prashanth Muralidhara ,  Sharada Venkateswaran ,  Daniel Liu ,  Nishant Singh ,  Bahaa Fahim ,  Samuel D. Strom

IPC: G06F12/0817

CPC classification number: G06F12/0817 ,  G06F2212/1021 ,  G06F2212/608

Abstract: A processor includes one or more cores having cache, a cache home agent (CHA), a near memory controller, to near memory, and a far memory controller, which is to: receive a first memory read operation from the CHA directed at a memory address; detect a miss for the first memory address at the near memory; issue a second memory read operation to the far memory controller to retrieve a cache line, having first data, from the memory address of far memory; receive the cache line from the far memory controller in response to the second memory read operation; and send the cache line to the CHA with a forced change to a directory state of the cache line at the CHA, the forced change to cause the CHA to snoop remote sockets to maintain data coherence for the cache line in an absence of directory state in the far memory.

公开(公告)号：US10782729B2

公开(公告)日：2020-09-22

申请号：US15827604

申请日：2017-11-30

Applicant: Intel Corporation

Inventor： Bahaa Fahim ,  Vedaraman Geetha ,  Don C. Soltis, Jr. ,  Samuel Strom ,  Jason Crop

IPC: G06F1/14 ,  G06F1/08 ,  G06F1/10 ,  G06F1/324 ,  G06F1/3234 ,  G06F9/22

Abstract: In an embodiment, a processor for clock signal modulation includes a clock source to generate a global clock signal, at least one processor component, a counter, and a circuit. The circuit is to: adjust the counter based on a level of activity of the at least one processor component; modulate, based on a value of the counter, the global clock signal to generate a modulated clock signal; and provide the modulated clock signal to the at least one processor component. Other embodiments are described and claimed.

公开(公告)号：US10534687B2

公开(公告)日：2020-01-14

申请号：US15639294

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Bahaa Fahim ,  Swadesh Choudhary

IPC: G06F11/30 ,  G06F11/34 ,  G06F11/14 ,  G06F11/36 ,  G06F11/07

Abstract: In one embodiment, a processor comprises a fabric interconnect to couple a first cache agent to at least one of a memory controller or an input/output (I/O) controller; and a first cache agent comprising a cache controller coupled to a cache; and a trace and capture engine to periodically capture a snapshot of state information associated with the first cache agent; trace events to occur at the first cache agent in between captured snapshots; and send the captured snapshots and traced events via the fabric interconnect to the memory controller or I/O controller for storage at a system memory or storage device.

公开(公告)号：US10514990B2

公开(公告)日：2019-12-24

申请号：US15823313

申请日：2017-11-27

Applicant: Intel Corporation

Inventor： Bahaa Fahim ,  Swadesh Choudhary ,  Rahul Pal ,  Vedaraman Geetha

IPC: G06F11/20 ,  G06F11/18 ,  G06F11/14 ,  G06F9/38

Abstract: Operational faults, including transient faults, are detected within computing hardware for mission-critical applications. Operational requests received from a requestor node are to be processed by shared agents to produce corresponding responses. A first request is duplicated to be redundantly processed independently and asynchronously by distinct shared agents to produce redundant counterpart responses including a first redundant response and a second redundant response. The first redundant response is compared against the second redundant response. In response to a match, the redundant responses are merged to produce a single final response to the first request to be read by the requestor node. In response to a non-match, an exception response is performed.

公开(公告)号：US20190163583A1

公开(公告)日：2019-05-30

申请号：US15823313

申请日：2017-11-27

Applicant: Intel Corporation

Inventor： Bahaa Fahim ,  Swadesh Choudhary ,  Rahul Pal ,  Vedaraman Geetha

IPC: G06F11/16 ,  G06F11/14 ,  G06F11/18

Abstract: Operational faults, including transient faults, are detected within computing hardware for mission-critical applications. Operational requests received from a requestor node are to be processed by shared agents to produce corresponding responses. A first request is duplicated to be redundantly processed independently and asynchronously by distinct shared agents to produce redundant counterpart responses including a first redundant response and a second redundant response. The first redundant response is compared against the second redundant response. In response to a match, the redundant responses are merged to produce a single final response to the first request to be read by the requestor node. In response to a non-match, an exception response is performed.

公开(公告)号：US10248591B2

公开(公告)日：2019-04-02

申请号：US15393153

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Robert J. Safranek ,  Robert G. Blankenship ,  Venkatraman Iyer ,  Jeff Willey ,  Robert H. Beers ,  Darren S. Jue ,  Arvind A. Kumar ,  Debendra Das Sharma ,  Jeffrey C. Swanson ,  Bahaa Fahim ,  Vedaraman Geetha ,  Aaron T. Spink ,  Fulvio Spagna ,  Rahul R. Shah ,  Sitaraman V. Iyer ,  William Harry Nale ,  Abhishek Das ,  Simon P. Johnson ,  Yuvraj S. Dhillon ,  Yen-Cheng Liu ,  Raj K. Ramanujan ,  Robert A. Maddox ,  Herbert H. Hum ,  Ashish Gupta

IPC: G06F13/22 ,  G06F12/0831 ,  G06F13/42 ,  G06F8/71 ,  G06F8/77 ,  G06F9/30 ,  G06F12/0806 ,  H04L12/933 ,  G06F9/46 ,  G06F13/40 ,  G06F12/0813 ,  G06F12/0815 ,  G06F9/445 ,  G06F1/3287 ,  G06F11/10 ,  H04L9/06 ,  G06F12/0808 ,  H04L12/741 ,  G06F8/73 ,  H04L12/46

Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

公开(公告)号：US20170109286A1

公开(公告)日：2017-04-20

申请号：US15393577

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Robert G. Blankenship ,  Bahaa Fahim ,  Robert H. Beers ,  Yen-Cheng Liu ,  Vedaraman Geetha ,  Herbert H. Hum ,  Jeff Willey

IPC: G06F12/0831 ,  G06F12/0808

CPC classification number: G06F13/22 ,  G06F1/3287 ,  G06F8/71 ,  G06F8/73 ,  G06F8/77 ,  G06F9/30145 ,  G06F9/44505 ,  G06F9/466 ,  G06F11/1004 ,  G06F12/0806 ,  G06F12/0808 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0833 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/4273 ,  G06F13/4282 ,  G06F13/4286 ,  G06F13/4291 ,  G06F2212/1016 ,  G06F2212/2542 ,  G06F2212/622 ,  H04L9/0662 ,  H04L12/4641 ,  H04L45/74 ,  H04L49/15 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151 ,  Y02D10/40 ,  Y02D10/44 ,  Y02D30/30

Abstract: A request is received that is to reference a first agent and to request a particular line of memory to be cached in an exclusive state. A snoop request is sent intended for one or more other agents. A snoop response is received that is to reference a second agent, the snoop response to include a writeback to memory of a modified cache line that is to correspond to the particular line of memory. A complete is sent to be addressed to the first agent, wherein the complete is to include data of the particular line of memory based on the writeback.

公开(公告)号：US09606925B2

公开(公告)日：2017-03-28

申请号：US14669248

申请日：2015-03-26

Applicant: Intel Corporation

Inventor： Bahaa Fahim ,  Yen-Cheng Liu ,  Vedaraman Geetha ,  Jeffrey D. Chamberlain ,  Min Huang

IPC: G06F12/00 ,  G06F12/08 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F12/0855 ,  G06F12/0817 ,  G06F12/0831 ,  G06F2212/27 ,  G06F2212/621 ,  Y02D10/13

Abstract: In one embodiment, a processor includes a caching home agent (CHA) coupled to a core and a cache memory and includes a cache controller having a cache pipeline and a home agent having a home agent pipeline. The CHA may: receive, in the home agent pipeline, information from an external agent responsive to a miss for data in the cache memory; issue a global ordering signal from the home agent pipeline to a requester of the data to inform the requester of receipt of the data; and report issuance of the global ordering signal to the cache pipeline, to prevent the cache pipeline from issuance of a global ordering signal to the requester. Other embodiments are described and claimed.