公开(公告)号：US09632862B2

公开(公告)日：2017-04-25

申请号：US14578413

申请日：2014-12-20

Applicant: Intel Corporation

Inventor： Brian S. Morris ,  Bill Nale ,  Robert G. Blankenship ,  Eric L. Hendrickson

IPC: G06F11/00 ,  G06F11/08 ,  G06F11/16 ,  G06F13/00 ,  H04L1/00 ,  H04L1/18

CPC classification number: G06F11/08 ,  G06F11/1625 ,  G06F11/1654 ,  G06F11/167 ,  G06F13/00 ,  H04L1/00 ,  H04L1/0061 ,  H04L1/0082 ,  H04L1/1838 ,  H04L2001/0097

Abstract: Data is sent from a memory buffer device to a host device over a link. An error in the data is determined. A read response cancellation signal is sent to the host device to indicate the error to the host device, where the read response cancellation signal is to be sent subsequent to the data being sent from the memory buffer device to the host device.

公开(公告)号：US20170091119A1

公开(公告)日：2017-03-30

申请号：US14865304

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Siddhartha Chhabra ,  Binata Bhattacharyya ,  Raghunandan Makaram ,  Brian S. Morris

IPC: G06F12/14 ,  H04L9/30 ,  G06F12/0802 ,  H04L9/32

CPC classification number: G06F12/1408 ,  G06F12/08 ,  G06F12/0802 ,  G06F12/1466 ,  G06F2212/1052 ,  G06F2212/402 ,  G06F2212/60 ,  H04L9/0637 ,  H04L9/30 ,  H04L9/3242

Abstract: A server, processing device and/or processor includes a processing core and a memory controller, operatively coupled to the processing core, to access data in an off-chip memory. A memory encryption engine (MEE) may be operatively coupled to the memory controller and the off-chip memory. The MEE may store non-MEE metadata bits within a modified version line corresponding to ones of a plurality of data lines stored in a protected region of the off-chip memory, compute an embedded message authentication code (eMAC) using the modified version line, and detect an attempt to modify one of the non-MEE metadata bits by using the eMAC within a MEE tree walk to authenticate access to the plurality of data lines. The non-MEE metadata bits may store coherence bits that track changes to a cache line in a remote socket, poison bits that track error containment within the data lines, and possibly other metadata bits.

公开(公告)号：US20160188500A1

公开(公告)日：2016-06-30

申请号：US14583147

申请日：2014-12-25

Applicant: Intel Corporation

Inventor： Brian S. Morris ,  Jeffrey C. Swanson ,  Bill Nale ,  Robert G. Blankenship ,  Jeff Willey ,  Eric L. Hendrickson

IPC: G06F13/16 ,  G11C7/10

CPC classification number: G06F13/1663 ,  G06F13/1673 ,  G11C5/04 ,  G11C7/10

Abstract: A plurality of completed writes to memory are identified corresponding to a plurality of write requests from a host device received over a buffered memory interface. A completion packet is sent to the host device that includes a plurality of write completions to correspond to the plurality of completed writes.

Abstract translation: 对存储器的多个完成的写入被识别为与通过缓冲存储器接口接收的主机设备的多个写入请求相对应。 完成分组被发送到主机设备，其包括多个写入完成以对应于多个完成的写入。

公开(公告)号：US12254061B2

公开(公告)日：2025-03-18

申请号：US17256195

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Maciej Urbanski ,  Brian J. Hickmann ,  Michael Rotzin ,  Krishnakumar Nair ,  Andrew Yang ,  Brian S. Morris ,  Dennis Bradford

IPC: G06F17/16 ,  G06F7/523 ,  G06F7/544

Abstract: Methods and apparatuses relating to performing vector multiplication are described. Hardware accelerators to perform vector multiplication are also described. In one embodiment, a combined fixed-point and floating-point vector multiplication circuit includes at least one switch to change the circuit between a first mode and a second mode, where in the first mode, each multiplier of a set of multipliers is to multiply mantissas from a same element position of a first floating-point vector and a second floating-point vector to produce a corresponding product, shift the corresponding products with a set of shift registers based on a maximum exponent of exponents for the corresponding products determined by a maximum exponent determiner to produce shifted products, perform an numeric conversion operation on the shifted products with a set of numeric conversion circuits based on sign bits from the same element position of the first floating-point vector and the second floating-point vector to produce signed representations of the shifted products, add the signed representations of the shifted products with a set of adders to produce a single product, and normalize the single product with a normalization circuit based on the maximum exponent into a single floating-point resultant, and in the second mode, each multiplier of the set of multipliers is to multiply values from a same element position of a first integer vector and a second integer vector to produce a corresponding product, and add each corresponding product with the set of adders to produce a single integer resultant.

公开(公告)号：US10042562B2

公开(公告)日：2018-08-07

申请号：US15684936

申请日：2017-08-23

Applicant: INTEL CORPORATION

Inventor： Vedaraman Geetha ,  Henk G. Neefs ,  Brian S. Morris ,  Sreenivas Mandava ,  Massimo Sutera

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/0866 ,  G06F12/0893

Abstract: Provided are an apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device having a 2n cache size. A request is to a target address having n bits directed to the second level memory device. A determination is made whether a target index, comprising m bits of the n bits of the target address, is within an index set of the first level memory device. A determination is made of a modified target index in the index set of the first level memory device having at least one index bit that differs from a corresponding at least one index bit in the target index. The request is processed with respect to data in a cache line at the modified target index in the first level memory device.

公开(公告)号：US20180067855A1

公开(公告)日：2018-03-08

申请号：US15665541

申请日：2017-08-01

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Michelle C. Jen ,  Brian S. Morris

IPC: G06F12/084 ,  G06F3/06 ,  G06F13/16 ,  G06F13/42

CPC classification number: G06F12/084 ,  G06F3/061 ,  G06F3/0635 ,  G06F3/0673 ,  G06F12/0806 ,  G06F12/0808 ,  G06F13/1673 ,  G06F13/4282 ,  G06F2212/1016 ,  G06F2212/60 ,  G06F2212/62

Abstract: A shared memory controller receives a flit from another first shared memory controller over a shared memory link, where the flit includes a node identifier (ID) field and an address of a particular line of the shared memory. The node ID field identifies that the first shared memory controller corresponds to a source of the flit. Further, a second shared memory controller is determined from at least the address field of the flit, where the second shared memory controller is connected to a memory element corresponding to the particular line. The flit is forwarded to the second shared memory controller using a shared memory link according to a routing path

公开(公告)号：US09824754B2

公开(公告)日：2017-11-21

申请号：US15000643

申请日：2016-01-19

Applicant: INTEL CORPORATION

Inventor： Sreenivas Mandava ,  Brian S. Morris ,  Suneeta Sah ,  Roy M. Stevens ,  Ted Rossin ,  Mathew W. Stefaniw ,  John H. Crawford

IPC: G11C7/02 ,  G11C11/406 ,  G06F12/10 ,  G11C14/00

CPC classification number: G11C14/0009 ,  G06F12/10 ,  G06F2212/1032 ,  G11C7/02 ,  G11C11/406

Abstract: Examples are disclosed for determining a logical address of one or more victim rows of a volatile memory based on a logical address of an aggressor row and address translation schemes associated with the volatile memory. Other examples are described and claimed.

公开(公告)号：US09747041B2

公开(公告)日：2017-08-29

申请号：US14757926

申请日：2015-12-23

Applicant: INTEL CORPORATION

Inventor： Vedaraman Geetha ,  Henk G. Neefs ,  Brian S. Morris ,  Sreenivas Mandava ,  Massimo Sutera

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/0893 ,  G06F12/0866

CPC classification number: G06F3/0611 ,  G06F3/0638 ,  G06F3/068 ,  G06F12/0866 ,  G06F12/0893 ,  G06F2212/1021 ,  G06F2212/205 ,  G06F2212/2532 ,  G06F2212/45 ,  G06F2212/60

Abstract: Provided are an apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device having a 2n cache size. A request is to a target address having n bits directed to the second level memory device. A determination is made whether a target index, comprising m bits of the n bits of the target address, is within an index set of the first level memory device. A determination is made of a modified target index in the index set of the first level memory device having at least one index bit that differs from a corresponding at least one index bit in the target index. The request is processed with respect to data in a cache line at the modified target index in the first level memory device.

公开(公告)号：US09720838B2

公开(公告)日：2017-08-01

申请号：US14670578

申请日：2015-03-27

Applicant: Intel Corporation

Inventor： Debendra Das Sharma ,  Michelle C. Jen ,  Brian S. Morris

IPC: G06F12/00 ,  G06F12/084 ,  G06F3/06 ,  G06F13/16 ,  G06F13/42

CPC classification number: G06F12/084 ,  G06F3/061 ,  G06F3/0635 ,  G06F3/0673 ,  G06F12/0806 ,  G06F12/0808 ,  G06F13/1673 ,  G06F13/4282 ,  G06F2212/1016 ,  G06F2212/60 ,  G06F2212/62

Abstract: A shared memory controller receives a flit from another first shared memory controller over a shared memory link, where the flit includes a node identifier (ID) field and an address of a particular line of the shared memory. The node ID field identifies that the first shared memory controller corresponds to a source of the flit. Further, a second shared memory controller is determined from at least the address field of the flit, where the second shared memory controller is connected to a memory element corresponding to the particular line. The flit is forwarded to the second shared memory controller using a shared memory link according to a routing path.

公开(公告)号：US09613722B2

公开(公告)日：2017-04-04

申请号：US14497834

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： George H. Huang ,  Debaleena Das ,  Brian S. Morris ,  Rajat Agarwal

IPC: G06F11/00 ,  G11C29/00 ,  G06F11/07

CPC classification number: G11C29/883 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/0793 ,  G06F11/1666 ,  G06F11/2094

Abstract: An apparatus and method are described for performing forward and reverse memory sparing operations. For example, one embodiment of a processor comprises memory sparing logic to perform a first forward memory sparing operation at a first level of granularity in response to detecting a memory failure; the memory sparing logic to perform a reverse memory sparing operation in response to a determination of an improved sparing state having a second level of granularity; and the memory sparing logic to responsively perform a second forward memory sparing operation at the second level of granularity.