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公开(公告)号:US10601738B2
公开(公告)日:2020-03-24
申请号:US16024774
申请日:2018-06-30
Applicant: Intel Corporation
Inventor: Bruce Richardson , Chris MacNamara , Patrick Fleming , Tomasz Kantecki , Ciara Loftus , John J. Browne , Patrick Connor
IPC: H04L12/861 , H04L12/879
Abstract: Technologies for buffering received network packet data include a compute device with a network interface controller (NIC) configured to determine a packet size of a network packet received by the NIC and identify a preferred buffer size between a small buffer and a large buffer. The NIC is further configured to select, from the descriptor, a buffer pointer based on the preferred buffer size, wherein the buffer pointer comprises one of a small buffer pointer corresponding to a first physical address in memory allocated to the small buffer or a large buffer pointer corresponding to a second physical address in memory allocated to the large buffer. Additionally, the NIC is configured to store at least a portion of the network packet in the memory based on the selected buffer pointer. Other embodiments are described herein.
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公开(公告)号:US20190327190A1
公开(公告)日:2019-10-24
申请号:US16460424
申请日:2019-07-02
Applicant: Intel Corporation
Inventor: John J. Browne , Tomasz Kantecki , Chris MacNamara , Pierre Laurent , Sean Harte
IPC: H04L12/879 , H04L12/46 , H04L12/861 , H04L12/43 , H04L12/927 , H04L12/935
Abstract: Technologies for scalable packet reception and transmission include a network device. The network device is to establish a ring that is defined as a circular buffer and includes a plurality of slots to store entries representative of packets. The network device is also to generate and assign receive descriptors to the slots in the ring. Each receive descriptor includes a pointer to a corresponding memory buffer to store packet data. The network device is further to determine whether the NIC has received one or more packets and copy, with direct memory access (DMA) and in response to a determination that the NIC has received one or more packets, packet data of the received one or more packets from the NIC to the memory buffers associated with the receive descriptors assigned to the slots in the ring.
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公开(公告)号:US20180373287A1
公开(公告)日:2018-12-27
申请号:US15632000
申请日:2017-06-23
Applicant: Intel Corporation
Inventor: Asma H. Al-Rawi , Federico Ardanaz , Jonathan M. Eastep , Dorit Shapira , Krishnakanth Sistla , Nikhil Gupta , Vasudevan Srinivasan , Chris MacNamara
Abstract: An apparatus system is provided which comprises: a first component and a second component; a first circuitry to assign the first component to a first group of components, and to assign the second component to a second group of components; and a second circuitry to assign a first maximum frequency limit to the first group of components, and to assign a second maximum frequency limit to the second group of components, wherein the first component and the second component are to respectively operate in accordance with the first maximum frequency limit and the second maximum frequency limit.
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公开(公告)号:US20180183659A1
公开(公告)日:2018-06-28
申请号:US15390329
申请日:2016-12-23
Applicant: Intel Corporation
Inventor: Chris MacNamara , Mark D. Gray , Andrew Cunningham , Pierre Laurent
IPC: H04L12/24 , H04L12/931
Abstract: Examples include techniques for a configuration mechanism of a virtual switch. Example techniques include monitoring a database including parameter to configure a virtual switch at a computing platform hosting a plurality of virtual machines or containers. Changes to one or more parameters may cause changes in allocations of computing resources associated with supporting the virtual switch.
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公开(公告)号:US20180004693A1
公开(公告)日:2018-01-04
申请号:US15198714
申请日:2016-06-30
Applicant: Intel Corporation
Inventor: Chris MacNamara , Tomasz Kantecki , John J. Browne
CPC classification number: G06F13/28 , G06T1/20 , G06T2200/28
Abstract: Discloses is an apparatus including a network interface controller (NIC), memory, and an accelerator. The accelerator can include a direct memory access (DMA) controller configured to receive data packets from the NIC and to provide the data packets to the memory. The accelerator can also include processing circuitry to generate processed data packets by implementing packet processing functions on the data packets received from the NIC, and to provide the processed data packets to at least one processing core. Other methods, apparatuses, articles and systems are also described
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公开(公告)号:US20170351311A1
公开(公告)日:2017-12-07
申请号:US15175144
申请日:2016-06-07
Applicant: INTEL CORPORATION
Inventor: Chris MacNamara , John J. Browne
IPC: G06F1/28 , H04L12/935 , G06F1/32
CPC classification number: G06F1/28 , G06F1/3243 , G06F1/3287 , G06F1/329 , G06F9/5094 , H04L49/3018 , Y02D10/152 , Y02D10/171 , Y02D10/24
Abstract: Disclosed herein is a computing device configured to implement power aware packet distribution. The computing device includes a central processing unit (CPU) comprising a plurality of cores and an interface controller communicatively coupled to the CPU. The interface controller is configured to receive a data packet to be sent to a targeted core of the plurality of cores and identify a power state of the targeted core. The interface controller is configured to redirect the data packet to an alternate core based on the power state of the targeted core.
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公开(公告)号:US12210632B2
公开(公告)日:2025-01-28
申请号:US17083149
申请日:2020-10-28
Applicant: Intel Corporation
Inventor: Sundar Vedantham , Bin Lin , Pravin Pathak , Ximing Chen , Chris MacNamara
Abstract: Examples described herein relate to a manner of provide a time of life of data. In some examples, data and control parameters are received from a data source. The data can be encrypted and stored. In addition, at least a portion of the control parameters can be stored into a distributed ledger. In some examples, the portion of the control parameters include an indicator of expiration time of the data. In some examples, a data header for the data is generated, where the data header includes an indication that the data is subject to a limited life span and a data identifier. The data header can be accessed with a request to access the encrypted data. In some examples, a request to determine if the data is valid and accessible is provided to a node of the distributed ledger and an indication of whether the data is valid and accessible is received from a node in the distributed ledger.
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18.
公开(公告)号:US11855897B2
公开(公告)日:2023-12-26
申请号:US17356420
申请日:2021-06-23
Applicant: Intel Corporation
Inventor: Patrick Connor , Andrey Chilikin , Brendan Ryan , Chris MacNamara , John J. Browne , Krishnamurthy Jambur Sathyanarayana , Stephen Doyle , Tomasz Kantecki , Anthony Kelly , Ciara Loftus , Fiona Trahe
IPC: H04W56/00 , H04L47/125 , G06F9/455 , H04L47/2441 , H04L43/0817 , G06F8/76
CPC classification number: H04L47/125 , G06F8/76 , G06F9/455 , H04L43/0817 , H04L47/2441
Abstract: A computing device includes an appliance status table to store at least one of reliability and performance data for one or more network functions virtualization (NFV) appliances and one or more legacy network appliances. The computing device includes a load controller to configure an Internet Protocol (IP) filter rule to select a packet for which processing of the packet is to be migrated from a selected one of the one or more legacy network appliances to a selected one of the one or more NFV appliances, and to update the appliance status table with received at least one of reliability and performance data for the one or more legacy network appliances and the one or more NFV appliances. The computing device includes a packet distributor to receive the packet, to select one of the one or more NFV appliances based at least in part on the appliance status table, and to send the packet to the selected NFV appliance. Other embodiments are described herein.
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公开(公告)号:US11847008B2
公开(公告)日:2023-12-19
申请号:US15951391
申请日:2018-04-12
Applicant: Intel Corporation
Inventor: David Hunt , Niall Power , Kevin Devey , Changzheng Wei , Bruce Richardson , Eliezer Tamir , Andrew Cunningham , Chris MacNamara , Nemanja Marjanovic , Rory Sexton , John Browne
IPC: G06F1/00 , G06F1/3228 , G06F1/3296 , G06F15/00 , G06F1/324
CPC classification number: G06F1/3228 , G06F1/324 , G06F1/3296 , G06F15/00
Abstract: Technologies for providing efficient detection of idle poll loops include a compute device. The compute device has a compute engine that includes a plurality of cores and a memory. The compute engine is to determine a ratio of unsuccessful operations to successful operations over a predefined time period of a core of the plurality cores that is assigned to continually poll, within the predefined time period, a memory address for a change in status and determine whether the determined ratio satisfies a reference ratio of unsuccessful operations to successful operations. The reference ratio is indicative of a change in the operation of the assigned core. The compute engine is further to selectively increase or decrease a power usage of the assigned core as a function of whether the determined ratio satisfies the reference ratio. Other embodiments are also described and claimed.
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公开(公告)号:US11671382B2
公开(公告)日:2023-06-06
申请号:US15185864
申请日:2016-06-17
Applicant: Intel Corporation
Inventor: John J. Browne , Seán Harte , Tomasz Kantecki , Pierre Laurent , Chris MacNamara
IPC: H04N21/443 , H04L49/9057 , H04N21/426 , H04L49/103 , H04L1/00 , H04L49/102 , H04L49/00 , H04L49/9005 , H04N21/232
CPC classification number: H04L49/9057 , H04L1/0016 , H04L49/102 , H04L49/103 , H04L49/3063 , H04N21/42692 , H04N21/4435 , H04L1/002 , H04L49/9005 , H04N21/2326
Abstract: Technologies for coordinating access to packets include a network device. The network device is to establish a ring in a memory of the network device. The ring includes a plurality of slots. The network device is also to allocate cores to each of an input stage, an output stage, and a worker stage. The worker stage is to process data in a data packet with an associated worker function. The network device is also to add, with the input stage, an entry to a slot in the ring representative of a data packet received with a network interface controller of the network device, access, with the worker stage, the entry in the ring to process at least a portion of the data packet, and provide, with the output stage, the processed data packet to the network interface controller for transmission.
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