Technologies for buffering received network packet data

    公开(公告)号:US10601738B2

    公开(公告)日:2020-03-24

    申请号:US16024774

    申请日:2018-06-30

    Abstract: Technologies for buffering received network packet data include a compute device with a network interface controller (NIC) configured to determine a packet size of a network packet received by the NIC and identify a preferred buffer size between a small buffer and a large buffer. The NIC is further configured to select, from the descriptor, a buffer pointer based on the preferred buffer size, wherein the buffer pointer comprises one of a small buffer pointer corresponding to a first physical address in memory allocated to the small buffer or a large buffer pointer corresponding to a second physical address in memory allocated to the large buffer. Additionally, the NIC is configured to store at least a portion of the network packet in the memory based on the selected buffer pointer. Other embodiments are described herein.

    TECHNOLOGIES FOR SCALABLE PACKET RECEPTION AND TRANSMISSION

    公开(公告)号:US20190327190A1

    公开(公告)日:2019-10-24

    申请号:US16460424

    申请日:2019-07-02

    Abstract: Technologies for scalable packet reception and transmission include a network device. The network device is to establish a ring that is defined as a circular buffer and includes a plurality of slots to store entries representative of packets. The network device is also to generate and assign receive descriptors to the slots in the ring. Each receive descriptor includes a pointer to a corresponding memory buffer to store packet data. The network device is further to determine whether the NIC has received one or more packets and copy, with direct memory access (DMA) and in response to a determination that the NIC has received one or more packets, packet data of the received one or more packets from the NIC to the memory buffers associated with the receive descriptors assigned to the slots in the ring.

    GRAPHICS PROCESSING UNIT (GPU) AS A PROGRAMMABLE PACKET TRANSFER MECHANISM

    公开(公告)号:US20180004693A1

    公开(公告)日:2018-01-04

    申请号:US15198714

    申请日:2016-06-30

    CPC classification number: G06F13/28 G06T1/20 G06T2200/28

    Abstract: Discloses is an apparatus including a network interface controller (NIC), memory, and an accelerator. The accelerator can include a direct memory access (DMA) controller configured to receive data packets from the NIC and to provide the data packets to the memory. The accelerator can also include processing circuitry to generate processed data packets by implementing packet processing functions on the data packets received from the NIC, and to provide the processed data packets to at least one processing core. Other methods, apparatuses, articles and systems are also described

    Transient dataset management system

    公开(公告)号:US12210632B2

    公开(公告)日:2025-01-28

    申请号:US17083149

    申请日:2020-10-28

    Abstract: Examples described herein relate to a manner of provide a time of life of data. In some examples, data and control parameters are received from a data source. The data can be encrypted and stored. In addition, at least a portion of the control parameters can be stored into a distributed ledger. In some examples, the portion of the control parameters include an indicator of expiration time of the data. In some examples, a data header for the data is generated, where the data header includes an indication that the data is subject to a limited life span and a data identifier. The data header can be accessed with a request to access the encrypted data. In some examples, a request to determine if the data is valid and accessible is provided to a node of the distributed ledger and an indication of whether the data is valid and accessible is received from a node in the distributed ledger.

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