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    WRAP-AROUND SOURCE/DRAIN METHOD OF MAKING CONTACTS FOR BACKSIDE METALS
    14.
    发明申请
    WRAP-AROUND SOURCE/DRAIN METHOD OF MAKING CONTACTS FOR BACKSIDE METALS 有权

    公开(公告)号：US20220140128A1

    公开(公告)日：2022-05-05

    申请号：US17578847

    申请日：2022-01-19

    Applicant: Intel Corporation

    Inventor： Patrick MORROW ,  Kimin JUN ,  Il-Seok SON ,  Donald W. NELSON

    IPC: H01L29/78 ,  H01L23/14 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01L29/417

    Abstract: An apparatus including a circuit structure including a first side including a device layer including a plurality of devices and an opposite second side; an electrically conductive contact coupled to one of the plurality of devices on the first side; and an electrically conductive interconnect disposed on the second side of the structure and coupled to the conductive contact. A method including forming a transistor device including a channel between a source and a drain and a gate electrode on the channel defining a first side of the device; forming an electrically conductive contact to one of the source and the drain from the first side; and forming an interconnect on a second side of the device, wherein the interconnect is coupled to the contact.

    WRAP-AROUND SOURCE/DRAIN METHOD OF MAKING CONTACTS FOR BACKSIDE METALS
    15.
    发明申请
    WRAP-AROUND SOURCE/DRAIN METHOD OF MAKING CONTACTS FOR BACKSIDE METALS 有权

    公开(公告)号：US20220140127A1

    公开(公告)日：2022-05-05

    申请号：US17578259

    申请日：2022-01-18

    Applicant: Intel Corporation

    Inventor： Patrick MORROW ,  Kimin JUN ,  Il-Seok SON ,  Donald W. NELSON

    IPC: H01L29/78 ,  H01L23/14 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L29/417

    Abstract: An apparatus including a circuit structure including a first side including a device layer including a plurality of devices and an opposite second side; an electrically conductive contact coupled to one of the plurality of devices on the first side; and an electrically conductive interconnect disposed on the second side of the structure and coupled to the conductive contact. A method including forming a transistor device including a channel between a source and a drain and a gate electrode on the channel defining a first side of the device; forming an electrically conductive contact to one of the source and the drain from the first side; and forming an interconnect on a second side of the device, wherein the interconnect is coupled to the contact.

    METAL ON BOTH SIDES WITH CLOCK GATED-POWER AND SIGNAL ROUTING UNDERNEATH
    16.
    发明申请
    METAL ON BOTH SIDES WITH CLOCK GATED-POWER AND SIGNAL ROUTING UNDERNEATH 审中-公开
    金属在具有时钟门控功率和信号路由的两面上

    公开(公告)号：US20170077030A1

    公开(公告)日：2017-03-16

    申请号：US15122913

    申请日：2014-09-27

    Applicant: Intel Corporation

    Inventor： Donald W. NELSON ,  Patrick MORROW ,  Kimin JUN

    IPC: H01L23/528 ,  H01L29/78 ,  H01L23/00 ,  H01L21/768

    CPC classification number: H01L23/5283 ,  H01L21/76838 ,  H01L24/14 ,  H01L29/78 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A method including forming a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein the plurality of second interconnects include interconnects of different dimensions; and forming contact points to the second plurality of interconnects, the contact points operable for connection to an external source. An apparatus including a substrate including a plurality of first interconnects and a plurality of second interconnects on opposite sides of an integrated circuit device layer including a plurality of circuit devices, wherein the plurality of second interconnects include interconnects of different dimensions; and contact points coupled to the second plurality of interconnects, the contact points operable for connection to an external source.

    Abstract translation: 一种包括在包括多个电路装置的集成电路装置层的相对侧上形成多个第一互连和多个第二互连的方法，其中所述多个第二互连包括不同尺寸的互连; 以及形成与所述第二多个互连件的接触点，所述接触点可操作以连接到外部源。 一种包括在包括多个电路器件的集成电路器件层的相对侧上包括多个第一互连和多个第二互连的衬底的器件，其中所述多个第二互连包括不同尺寸的互连; 以及耦合到第二多个互连的接触点，所述接触点可操作用于连接到外部源。

    METHOD FOR DIRECT INTEGRATION OF MEMORY DIE TO LOGIC DIE WITHOUT USE OF THRU SILICON VIAS (TSV)
    17.
    发明申请
    METHOD FOR DIRECT INTEGRATION OF MEMORY DIE TO LOGIC DIE WITHOUT USE OF THRU SILICON VIAS (TSV) 审中-公开
    无需使用硅橡胶（TSV）将记忆体直接集成到逻辑芯片上的方法

    公开(公告)号：US20170069598A1

    公开(公告)日：2017-03-09

    申请号：US15122630

    申请日：2014-06-16

    Applicant: Intel Corporation

    Inventor： Donald W. NELSON ,  M Clair WEBB ,  Patrick MORROW ,  Kimin JUN

    IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L23/538

    CPC classification number: H01L25/0652 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/06 ,  H01L24/17 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/1436 ,  H01L2924/00

    Abstract: A method including forming a first substrate including an integrated circuit device layer disposed between a plurality of first interconnects and a plurality of second interconnects; coupling a second substrate including a memory device layer to the first substrate so that the memory device layer is juxtaposed to one of the plurality of first interconnects and the plurality of second interconnects; and removing a portion of the first substrate. An apparatus including a device layer including a plurality of circuit devices disposed between a plurality of first interconnects and a plurality of second interconnects on a substrate; a memory device layer including a plurality of memory devices juxtaposed and coupled to one of the plurality of first interconnects and the plurality of second interconnects; and contacts points coupled to one of ones of the first plurality of interconnects and ones of the second plurality of interconnects.

    Abstract translation: 一种包括形成第一衬底的方法，所述第一衬底包括设置在多个第一互连和多个第二互连之间的集成电路器件层; 将包括存储器件层的第二衬底耦合到所述第一衬底，使得所述存储器件层与所述多个第一互连和所述多个第二互连中的一个并置; 以及去除所述第一基板的一部分。 一种装置，包括：器件层，包括设置在基板上的多个第一互连和多个第二互连之间的多个电路器件; 存储器件层，包括并置并耦合到所述多个第一互连和所述多个第二互连中的一个的多个存储器件; 以及联接到所述第一多个互连中的一个和所述第二多个互连中的一个的接触点。

    SILICON DIE WITH INTEGRATED HIGH VOLTAGE DEVICES
    18.
    发明申请
    SILICON DIE WITH INTEGRATED HIGH VOLTAGE DEVICES 审中-公开
    具有集成高压设备的硅芯片

    公开(公告)号：US20170069597A1

    公开(公告)日：2017-03-09

    申请号：US15122382

    申请日：2014-06-16

    Applicant: Intel Corporation

    Inventor： Donald W. NELSON ,  M. Clair WEBB ,  Patrick MORROW ,  Kimin JUN

    IPC: H01L25/065 ,  H01L21/683 ,  H01L23/00 ,  H01L25/00 ,  H01L23/498 ,  H01L23/538

    Abstract: A method including forming a plurality of first devices and a plurality of first interconnects on a substrate; coupling a second device layer including a plurality of second devices to ones of the plurality of first interconnects, and forming a plurality of second interconnects on the second device layer. An apparatus including a first device layer including a plurality of first circuit devices disposed between a plurality of first interconnects and a plurality of second interconnects and a second device layer including a plurality of second devices juxtaposed and coupled to one of the plurality of first interconnects and the plurality of second interconnects, wherein one of the plurality of first devices and the plurality of second devices include devices having a higher voltage range than the other of the plurality of first devices and the plurality of second devices.

    Abstract translation: 一种方法，包括在衬底上形成多个第一器件和多个第一互连件; 将包括多个第二设备的第二设备层耦合到所述多个第一互连中的一个，并且在所述第二设备层上形成多个第二互连。 一种包括第一装置层的装置，包括设置在多个第一互连和多个第二互连之间的多个第一电路装置和包括多个第二装置的第二装置层，所述第二装置层并置并耦合到所述多个第一互连中的一个， 所述多个第二互连，其中所述多个第一装置和所述多个第二装置中的一个包括具有比所述多个第一装置和所述多个第二装置中的另一个更高的电压范围的装置。

    POWER GATE WITH METAL ON BOTH SIDES
    19.
    发明申请
    POWER GATE WITH METAL ON BOTH SIDES 有权

    公开(公告)号：US20220181456A1

    公开(公告)日：2022-06-09

    申请号：US17682804

    申请日：2022-02-28

    Applicant: Intel Corporation

    Inventor： Donald W. NELSON

    IPC: H01L29/417 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

    Abstract: An apparatus including a circuit structure including a device stratum including a plurality of transistor devices each including a first side defined by a gate electrode and an opposite second side; and a gated supply grid disposed on the second side of the structure, wherein a drain of the at least one of the plurality of transistor devices is coupled to the gated supply grid. A method including providing a supply from a package substrate to power gate transistors in a device layer of a circuit structure, the transistors coupled to circuitry operable to receive a gated supply from the power gate transistors; and distributing the gated supply from the power gate transistors to the circuitry using a grid on an underside of the device layer.

    METAL ON BOTH SIDES WITH POWER DISTRIBUTED THROUGH THE SILICON
    20.
    发明申请
    METAL ON BOTH SIDES WITH POWER DISTRIBUTED THROUGH THE SILICON 审中-公开

    公开(公告)号：US20190267316A1

    公开(公告)日：2019-08-29

    申请号：US16408314

    申请日：2019-05-09

    Applicant: Intel Corporation

    Inventor： Donald W. NELSON ,  Mark T. BOHR ,  Patrick MORROW

    IPC: H01L23/498 ,  H01L23/528 ,  H01L49/02

    Abstract: An apparatus including a circuit structure including a device stratum; and a contact coupled to a supply line and routed through the device stratum and coupled to at least one device on a first side. A method including providing a supply from a package substrate to at least one transistor in a device stratum of a circuit structure; and distributing the supply to the at least one transistor using a supply line on an underside of the device stratum and contacting the at least one transistor on a device side by routing a contact from the supply line through the device stratum. A system including a package substrate, and a die including at least one supply line disposed on an underside of a device stratum and routed through the device stratum and coupled to at least one of a plurality of transistor devices on the device side.

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