公开(公告)号：US11652047B2

公开(公告)日：2023-05-16

申请号：US16457641

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Travis W. Lajoie ,  Abhishek A. Sharma ,  Van H. Le ,  Chieh-Jen Ku ,  Pei-Hua Wang ,  Jack T. Kavalieros ,  Bernhard Sell ,  Tahir Ghani ,  Gregory George ,  Akash Garg ,  Julie Rollins ,  Allen B. Gardiner ,  Shem Ogadhoh ,  Juan G. Alzate Vinasco ,  Umut Arslan ,  Fatih Hamzaoglu ,  Nikhil Mehta ,  Ting Chen ,  Vinaykumar V. Hadagali

IPC: H01L23/528 ,  H01L23/522 ,  H01L27/108

CPC classification number: H01L23/528 ,  H01L23/5226 ,  H01L27/1085 ,  H01L27/10805 ,  H01L27/10873

Abstract: Embodiments herein describe techniques for a semiconductor device having an interconnect structure including an inter-level dielectric (ILD) layer between a first layer and a second layer of the interconnect structure. The interconnect structure further includes a separation layer within the ILD layer. The ILD layer includes a first area with a first height to extend from a first surface of the ILD layer to a second surface of the ILD layer. The ILD layer further includes a second area with a second height to extend from the first surface of the ILD layer to a surface of the separation layer, where the first height is larger than the second height. Other embodiments may be described and/or claimed.

公开(公告)号：US20220415896A1

公开(公告)日：2022-12-29

申请号：US17358930

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Juan G. Alzate-Vinasco ,  Travis W. LaJoie ,  Wilfred Gomes ,  Fatih Hamzaoglu ,  Pulkit Jain ,  James Waldemer ,  Mark Armstrong ,  Bernhard Sell ,  Pei-Hua Wang ,  Chieh-Jen Ku

IPC: H01L27/108 ,  H01L29/786 ,  H01L29/66

Abstract: A device structure includes transistors on a first level in a first region and a first plurality of capacitors on a second level, above the first level, where a first electrode of the individual ones of the first plurality of capacitors are coupled with a respective transistor. The device structure further includes a second plurality of capacitors on the second level in a second region adjacent the first region, where individual ones of the second plurality of capacitors include a second electrode, a third electrode and an insulator layer therebetween, where the second electrode of the individual ones of the plurality of capacitors are coupled with a first interconnect on a third level above the second level, and where the third electrode of the individual ones of the plurality of capacitors are coupled with a second interconnect.

公开(公告)号：US11462541B2

公开(公告)日：2022-10-04

申请号：US16222934

申请日：2018-12-17

Applicant: Intel Corporation

Inventor： Juan G. Alzate Vinasco ,  Abhishek A. Sharma ,  Fatih Hamzaoglu ,  Bernhard Sell ,  Pei-Hua Wang ,  Van H. Le ,  Jack T. Kavalieros ,  Tahir Ghani ,  Chieh-Jen Ku ,  Travis W. Lajoie ,  Umut Arslan

IPC: H01L21/00 ,  H01L27/108 ,  H01L29/786 ,  H01L49/02 ,  H01L29/66 ,  H01L29/49 ,  H01L29/417

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate oriented in a horizontal direction, and a memory cell including a transistor and a capacitor above the substrate. The transistor includes a gate electrode oriented in a vertical direction substantially orthogonal to the horizontal direction, and a channel layer oriented in the vertical direction, around the gate electrode and separated by a gate dielectric layer from the gate electrode. The capacitor is within an inter-level dielectric layer above the substrate. The capacitor includes a first plate coupled with a second portion of the channel layer of the transistor, and a second plate separated from the first plate by a capacitor dielectric layer. The first plate of the capacitor is also a source electrode of the transistor. Other embodiments may be described and/or claimed.

公开(公告)号：US11094358B2

公开(公告)日：2021-08-17

申请号：US16319239

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Ilya Karpov ,  Yih Wang ,  Fatih Hamzaoglu ,  James Clarke

IPC: H01L21/02 ,  G11C11/00 ,  G11C11/22 ,  G11C11/407 ,  H01L27/108 ,  H01L27/11514 ,  H01L27/11507 ,  G11C11/401

Abstract: An apparatus is described. The apparatus includes a semiconductor chip that includes logic circuitry, embedded dynamic random access memory (DRAM) cells and embedded ferroelectric random access memory (FeRAM) cells.

公开(公告)号：US10515697B1

公开(公告)日：2019-12-24

申请号：US16023728

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Pulkit Jain ,  Umut Arslan ,  Fatih Hamzaoglu

IPC: G11C13/00 ,  G11C7/06 ,  G11C8/10

Abstract: Some embodiments include apparatuses having a resistive memory device and methods to apply a combination of voltage stepping current stepping and pulse width stepping during an operation of changing a resistance of a memory cell of the resistive memory device. The apparatuses also include a write termination circuit to limit drive current provided to a memory cell of the resistive memory device during a particular time of an operation performed on the memory cell. The apparatuses further include a programmable variable resistor and resistor control circuit that operate during sensing operation of the memory device.

公开(公告)号：US11991873B2

公开(公告)日：2024-05-21

申请号：US18109780

申请日：2023-02-14

Applicant: Intel Corporation

Inventor： Travis W. Lajoie ,  Abhishek A. Sharma ,  Van H. Le ,  Chieh-Jen Ku ,  Pei-Hua Wang ,  Jack T. Kavalieros ,  Bernhard Sell ,  Tahir Ghani ,  Gregory George ,  Akash Garg ,  Julie Rollins ,  Allen B. Gardiner ,  Shem Ogadhoh ,  Juan G. Alzate Vinasco ,  Umut Arslan ,  Fatih Hamzaoglu ,  Nikhil Mehta ,  Yu-Wen Huang ,  Shu Zhou

IPC: H10B12/00

CPC classification number: H10B12/03 ,  H10B12/05 ,  H10B12/30

Abstract: Embodiments herein describe techniques for a semiconductor device including a substrate, a first inter-level dielectric (ILD) layer above the substrate, and a second ILD layer above the first ILD layer. A first capacitor and a second capacitor are formed within the first ILD layer and the second ILD layer. A first top plate of the first capacitor and a second top plate of the second capacitor are formed at a boundary between the first ILD layer and the second ILD layer. The first capacitor and the second capacitor are separated by a dielectric area in the first ILD layer. The dielectric area includes a first dielectric area that is coplanar with the first top plate or the second top plate, and a second dielectric area above the first dielectric area and to separate the first top plate and the second top plate. Other embodiments may be described and/or claimed.

公开(公告)号：US20230067765A1

公开(公告)日：2023-03-02

申请号：US17409877

申请日：2021-08-24

Applicant: INTEL CORPORATION

Inventor： Abhishek A. Sharma ,  Noriyuki Sato ,  Van H. Le ,  Sarah Atanasov ,  Hui Jae Yoo ,  Bernhard Sell ,  Pei-hua Wang ,  Travis W. Lajoie ,  Chieh-Jen Ku ,  Juan G. Alzate-Vinasco ,  Fatih Hamzaoglu

IPC: H01L23/00 ,  H01L25/065

Abstract: IC devices implementing bilayer stacking with lines shared between bottom and top memory layers, and associated systems and methods, are disclosed. An example IC device includes a support structure, a front end of line (FEOL) layer and a back end of line (BEOL) layer. The BEOL layer includes a first memory cell in a first layer over the support structure, an electrically conductive line in a second layer, above the first layer, and a second memory cell in a third layer, above the second layer. The line could be one of a wordline, a bitline, or a plateline that is shared between the first and second memory cells. In particular, bilayer stacking line sharing is such that only one line is provided as a line to be shared between one or more of the memory cells of the first layer and one or more memory cells of the third layer.

公开(公告)号：US20220406782A1

公开(公告)日：2022-12-22

申请号：US17351301

申请日：2021-06-18

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Albert B. Chen ,  Wilfred Gomes ,  Fatih Hamzaoglu ,  Travis W. Lajoie ,  Van H. Le ,  Alekhya Nimmagadda ,  Miriam R. Reshotko ,  Hui Jae Yoo

IPC: H01L27/108 ,  H01L29/06 ,  H01L23/528

Abstract: An example IC device includes a frontend layer and a backend layer with a metallization stack. The metallization stack includes a backend memory layer with a plurality of memory cells with backend transistors, and a layer with a plurality of conductive interconnects (e.g., a plurality of conductive lines) and air gaps between adjacent ones of the plurality of interconnects. Providing air gaps in upper metal layers of metallization stacks of IC devices may advantageously reduce parasitic effects in the IC devices because such effects are typically proportional to the dielectric constant of a surrounding medium. In turn, reduction in the parasitic effects may lead to improvements in performance of, or requirements placed on, the backend memory.

公开(公告)号：US20200035683A1

公开(公告)日：2020-01-30

申请号：US16043548

申请日：2018-07-24

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Juan G. Alzate-Vinasco ,  Fatih Hamzaoglu ,  Bernhard Sell ,  Pei-hua Wang ,  Van H. Le ,  Jack T. Kavalieros ,  Tahir Ghani ,  Umut Arslan ,  Travis W. Lajoie ,  Chieh-jen Ku

IPC: H01L27/108 ,  H01L27/06 ,  H01L25/065 ,  H01L29/786 ,  H01L23/00 ,  H01L29/417 ,  G11C11/407 ,  G11C7/06

Abstract: Described herein are arrays of embedded dynamic random-access memory (eDRAM) cells that use TFTs as selector transistors. When at least some selector transistors are implemented as TFTs, different eDRAM cells may be provided in different layers above a substrate, enabling a stacked architecture. An example stacked TFT based eDRAM includes one or more memory cells provided in a first layer over a substrate and one or more memory cells provided in a second layer, above the first layer, where at least the memory cells in the second layer, but preferably the memory cells in both the first and second layers, use TFTs as selector transistors. Stacked TFT based eDRAM allows increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.

公开(公告)号：US20170018298A1

公开(公告)日：2017-01-19

申请号：US15280935

申请日：2016-09-29

Applicant: Intel Corporation

Inventor： Cyrille Dray ,  Blake C. Lin ,  Fatih Hamzaoglu ,  Liqiong Wei ,  Yih Wang

IPC: G11C11/16 ,  G06F3/06

CPC classification number: G11C11/1675 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/067 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1697

Abstract: Described is an apparatus for improving read and write margins. The apparatus comprises: a sourceline; a first bitline; a column of resistive memory cells, each resistive memory cell of the column coupled at one end to the sourceline and coupled to the first bitline at another end; and a second bitline in parallel to the first bitline, the second bitline to decouple read and write operations on the bitline for the resistive memory cell. Described is also an apparatus which comprises: a sourceline; a bitline; a column of resistive memory cells, each resistive memory cell in the column coupled at one end to the sourceline and coupled to the bitline at another end; and sourceline write drivers coupled to the bitline and the sourceline, wherein the sourceline write drivers are distributed along the column of resistive memory cells.

Abstract translation: 描述了一种用于提高读写余量的装置。 该装置包括：源线; 第一个位线 一列电阻存储器单元，该列的每个电阻存储器单元在一端耦合到源极线并且在另一端耦合到第一位线; 以及与所述第一位线并联的第二位线，所述第二位线用于解耦所述电阻存储器单元的位线上的读取和写入操作。 还描述了一种装置，其包括：源线; 有位 一列电阻存储器单元，列中的每个电阻存储器单元在一端耦合到源极线并且在另一端耦合到位线; 以及耦合到位线和源极线的源极线写入驱动器，其中源极线写入驱动器沿着电阻存储器单元的列分布。