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公开(公告)号：US11048284B2
公开(公告)日：2021-06-29
申请号：US16566368
申请日：2019-09-10
Applicant: Intel Corporation
Inventor： Praveen Mosalikanti , Gerhard Schrom , Vaughn J. Grossnickle , Nasser A. Kurd
IPC: G05F1/625 , G01R19/165 , H03K5/24 , H03L7/093 , H03L7/06
Abstract: Some embodiments include apparatuses and methods of operating such apparatuses. One of the embodiments includes an input node to receive an input voltage, a circuit portion to generate first, second, and third voltages based on the input voltage, a comparator circuit to compare the first voltage with the second voltage to generate a first signal and to compare the first voltage with the third voltage to generate a second signal, and an output circuit to generate an output signal based on the first and second signals.
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公开(公告)号：US10976764B2
公开(公告)日：2021-04-13
申请号：US16575259
申请日：2019-09-18
Applicant: Intel Corporation
Inventor： Sergio Carlo Rodriguez , Alexander Lyakhov , Gerhard Schrom , Keith Hodgson , Sarath S. Makala , Sidhanto Roy
Abstract: A compensator is described with higher bandwidth than a traditional differential compensator, lower area than traditional differential compensator (e.g., 40% lower area), and lower power than traditional differential compensator. The compensator includes a differential to single-ended circuitry that reduces the number of passive devices used to compensate an input signal. The high bandwidth compensator allows for faster power state and/or voltage transitions. For example, a pre-charge technique is applied to handle faster power state transitions that enables aggressive dynamic voltage and frequency scaling (DVFS) and voltage transitions. The compensator is configurable in that it can operate in voltage mode or current mode.
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公开(公告)号：US10483249B2
公开(公告)日：2019-11-19
申请号：US16060658
申请日：2015-12-26
Applicant: Intel Corporation
Inventor： Donald S. Gardner , Edward A. Burton , Gerhard Schrom , Larry E. Mosley
Abstract: Embodiments are generally directed to integrated passive devices on chip. An embodiment of a device includes a semiconductor die; a semiconductor die package, a first side of the package being coupled with the semiconductor die; and one or more separate dies to provide passive components for operation of the semiconductor die, wherein the passive components for operation of the semiconductor die includes inductors.
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公开(公告)号：US20170133364A9
公开(公告)日：2017-05-11
申请号：US14738799
申请日：2015-06-12
Applicant: Intel Corporation
Inventor： Han Wui THEN , Sansaptak Dasgupta , Gerhard Schrom , Valluri R. Rao , Robert S. Chau
IPC: H01L27/06 , H01L29/04 , H01L29/20 , H01L29/10 , H01L29/205 , H01L29/94 , H01L29/778
CPC classification number: H01L27/0629 , H01L21/8252 , H01L21/8258 , H01L27/0605 , H01L29/04 , H01L29/045 , H01L29/0657 , H01L29/1095 , H01L29/2003 , H01L29/205 , H01L29/66181 , H01L29/7787 , H01L29/94 , H01L29/945
Abstract: III-N high voltage MOS capacitors and System on Chip (SoC) solutions integrating at least one III-N MOS capacitor capable of high breakdown voltages (BV) to implement high voltage and/or high power circuits. Breakdown voltages over 4V may be achieved avoiding any need to series couple capacitors in an RFIC and/or PMIC. In embodiments, depletion mode III-N capacitors including a GaN layer in which a two dimensional electron gas (2DEG) is formed at threshold voltages below 0V are monolithically integrated with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. In embodiments, silicon substrates are etched to provide a (111) epitaxial growth surface over which a GaN layer and III-N barrier layer are formed. In embodiments, a high-K dielectric layer is deposited, and capacitor terminal contacts are made to the 2DEG and over the dielectric layer.
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公开(公告)号：US20170117795A1
公开(公告)日：2017-04-27
申请号：US15402021
申请日：2017-01-09
Applicant: INTEL CORPORATION
Inventor： Gerhard Schrom , Naravanan Raghuraman , Fabrice Paillet
CPC classification number: H02M1/14 , G06F1/26 , H02M2003/1586 , H03H7/325 , H03H11/265 , H03K3/0315 , H03K4/06 , H03K5/133 , H03K5/134 , H03K7/08 , H03K2005/00019 , H03K2005/00195 , H03L7/00
Abstract: Described herein is an apparatus and system for generating a signal with phase angle configuration. The apparatus comprises an array of switch-resistors, each switch resistor to receive a control signal, wherein the array of switch-resistors to generate an output signal; and a circuit to configure phase angle of the output signal. The apparatus can be used for different package and inductor configurations. The apparatus provides flexibility to mitigate switching noise by adjusting phase angles, and provides the ability to enable and disable switch-resistors on the fly without ripples. The apparatus also saves power consumption by selectively turning off switch-resistors when phases are disabled. The output signal of the apparatus has smooth triangular waveforms for improving the quality of power supply generated using the output signal. Overall, the apparatus exhibits reduced sensitivity to process variations compared to traditional signal generators.
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Patent Agency Ranking
公开(公告)号：US20160239036A1
公开(公告)日：2016-08-18
申请号：US14621261
申请日：2015-02-12
Applicant: Intel Corporation
Inventor： Fabrice Paillet , Gerhard Schrom , Anant Deval , Rajan Vijayaraghavan
CPC classification number: G05F3/08 , G05F1/46 , G06F1/26 , H02M3/1584 , H02M2001/0045 , H02M2001/007 , H02M2001/008
Abstract: The present disclosure provides a power delivery scheme to provide a parallel regulation feature for integrated voltage regulators (IVRs).
Abstract translation: 本公开提供了为集成稳压器（IVR）提供并行调节特征的功率传递方案。
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公开(公告)号：US20210080987A1
公开(公告)日：2021-03-18
申请号：US16575259
申请日：2019-09-18
Applicant: Intel Corporation
Inventor： Sergio Carlo Rodriguez , Alexander Lyakhov , Gerhard Schrom , Keith Hodgson , Sarath S. Makala , Sidhanto Roy
Abstract: A compensator is described with higher bandwidth than a traditional differential compensator, lower area than traditional differential compensator (e.g., 40% lower area), and lower power than traditional differential compensator. The compensator includes a differential to single-ended circuitry that reduces the number of passive devices used to compensate an input signal. The high bandwidth compensator allows for faster power state and/or voltage transitions. For example, a pre-charge technique is applied to handle faster power state transitions that enables aggressive dynamic voltage and frequency scaling (DVFS) and voltage transitions. The compensator is configurable in that it can operate in voltage mode or current mode.
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18.发明授权公开(公告)号：US10651733B2
公开(公告)日：2020-05-12
申请号：US14810385
申请日：2015-07-27
Applicant: Intel Corporation
Inventor： Gerhard Schrom , Mark S. Milshtein , Alexander Lyakhov
Abstract: Described is an apparatus which comprises: a low-side switch coupled to an output node for providing regulated voltage supply; and a first driver operable to cause the low-side switch to turn off when the output node rises above a first transistor threshold voltage. Described is also a voltage regulator which comprises: a signal generator to generate a pulse-width modulated (PWM) signal; a bridge having a low-side switch coupled to an output node for providing regulated voltage supply according to the PWM signal; a first driver operable to cause the low-side switch to turn off when the output node rises above a first transistor threshold voltage; and a bridge controller to provide control signals to the first driver. The voltage regulator may operate without diode clamps and its operation is self-timed. The voltage regulator also provides tolerance against process variation.
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公开(公告)号：US10423182B2
公开(公告)日：2019-09-24
申请号：US15478457
申请日：2017-04-04
Applicant: Intel Corporation
Inventor： Praveen Mosalikanti , Gerhard Schrom , Vaughn J. Grossnickle , Nasser A. Kurd
IPC: G05F1/625 , H03L7/093 , H03K5/24 , G01R19/165
Abstract: Some embodiments include apparatuses and methods of operating such apparatuses. One of the embodiments includes an input node to receive an input voltage, a circuit portion to generate first, second, and third voltages based on the input voltage, a comparator circuit to compare the first voltage with the second voltage to generate a first signal and to compare the first voltage with the third voltage to generate a second signal, and an output circuit to generate an output signal based on the first and second signals.
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20.发明授权公开(公告)号：US10184961B2
公开(公告)日：2019-01-22
申请号：US15276697
申请日：2016-09-26
Applicant: Intel Corporation
Inventor： Gerhard Schrom , J. Keith Hodgson , Alexander Lyakhov , Chiu Keung Tang , Narayanan Raghuraman , Narayanan Natarajan
IPC: H03M1/66 , G01R19/00 , H02M3/157 , H03L5/00 , G06T3/40 , H02M3/156 , H02M1/088 , H02M3/158 , H03M1/68 , H02M1/00
Abstract: Described are apparatuses and methods of current balancing, current sensing and phase balancing, offset cancellation, digital to analog current converter with monotonic output using binary coded input (without binary to thermometer decoder), compensator for a voltage regulator (VR), etc. In one example, apparatus comprises: a plurality of inductors coupled to a capacitor and a load; a plurality of bridges, each of which is coupled to a corresponding inductor from the plurality of inductors; and a plurality of current sensors, each of which is coupled to a bridge to sense current through a transistor of the bridge.
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