公开(公告)号：US11169560B2

公开(公告)日：2021-11-09

申请号：US16480830

申请日：2017-02-24

Applicant: INTEL CORPORATION

Inventor： Vasudevan Srinivasan ,  Krishnakanth V. Sistla ,  Corey D. Gough ,  Ian M. Steiner ,  Nikhil Gupta ,  Vivek Garg ,  Ankush Varma ,  Sujal A. Vora ,  David P. Lerner ,  Joseph M. Sullivan ,  Nagasubramanian Gurumoorthy ,  William J. Bowhill ,  Venkatesh Ramamurthy ,  Chris Macnamara ,  John J. Browne ,  Ripan Das

IPC: G06G1/08 ,  G06F1/3203 ,  G06F9/30 ,  G06F9/455 ,  G06F1/324 ,  G06F1/08

Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.

公开(公告)号：US20200241980A1

公开(公告)日：2020-07-30

申请号：US16779152

申请日：2020-01-31

Applicant: Intel Corporation

Inventor： Eric J. DeHaemer ,  Arijit Biswas ,  Reid J. Riedlinger ,  Ian M. Steiner

IPC: G06F11/20

Abstract: A multicore processor may include multiple processing cores that were previously designated as active cores and at least one processing core that was previously designated as a functional spare. The processor may include an interface to receive, during operation of the processor in an end-user environment, a request to change the designation of at least one of the processing cores. The processor may be to store, into a desired cores configuration data structure in response to the request, data representing a bitmask that reflects the requested change, and to execute a reset sequence. During the reset sequence, the processor may activate, dependent on the bitmask, a processing core previously designated as a functional spare, or may deactivate, dependent on the bitmask, a processing core previously designated as an active core. The processor may include a predetermined maximum number of active cores and a predetermined minimum number of functional spares.

公开(公告)号：US10509455B2

公开(公告)日：2019-12-17

申请号：US15860300

申请日：2018-01-02

Applicant: Intel Corporation

Inventor： Corey D. Gough ,  Ian M. Steiner ,  Krishnakanth V. Sistla

IPC: G06F1/28 ,  G06F13/42 ,  G06F1/3228 ,  G06F1/3234 ,  G06F1/3296 ,  G06F1/3287

Abstract: A method is provided for controlling a link. This may include determining a condition of a first device coupled to the link, receiving, at the first device, a request for a specific link state from a second device coupled to the link, and determining a power state of the link based on the determined condition of the first device.

公开(公告)号：US10146287B2

公开(公告)日：2018-12-04

申请号：US15088531

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Federico Ardanaz ,  Ian M. Steiner ,  Jonathan M. Eastep ,  Richard J. Greco ,  Krishnakanth V. Sistla ,  Micah Barany ,  Andrew J. Herdrich

IPC: G06F1/32 ,  G06F1/28

Abstract: Apparatus and methods may provide for subscribing a thread to a resource monitor through a machine specific register and subscribing the thread to a class of service through the machine specific register. The resource monitor or the class of service for the thread may be changed without interrupting the thread. The power allocated to the processor core may be changed based on the selected class of service for the thread.

公开(公告)号：US09760409B2

公开(公告)日：2017-09-12

申请号：US15162709

申请日：2016-05-24

Applicant: Intel Corporation

Inventor： Krishnakanth V. Sistla ,  Mark Rowland ,  Ankush Varma ,  Ian M. Steiner ,  Matthew Bace ,  Daniel Borkowski ,  Vivek Garg ,  Chelsea Akturan ,  Avinash N. Ananthakrishnan

IPC: G06F1/32 ,  G06F9/50

CPC classification number: G06F9/5094 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/3287 ,  Y02D10/126 ,  Y02D10/171

Abstract: In one embodiment, the present invention includes a multicore processor having a power controller with logic to dynamically switch a power management policy from a power biased policy to a performance biased policy when a utilization of the processor exceeds a threshold level. Thus at low utilizations, reduced power consumption can be realized, while at higher utilizations, greater performance can be realized. Other embodiments are described and claimed.

公开(公告)号：US20170083076A1

公开(公告)日：2017-03-23

申请号：US15367330

申请日：2016-12-02

Applicant: Intel Corporation

Inventor： Krishnakanth V. Sistla ,  Jeremy Shrall ,  Stephen H. Gunther ,  Efraim Rotem ,  Alon Naveh ,  Eliezer Weissmann ,  Anil Aggarwal ,  Martin T. Rowland ,  Ankush Varma ,  Ian M. Steiner ,  Matthew Bace ,  Avinash N. Ananthakrishnan ,  Jason Brandt

IPC: G06F1/32 ,  G06F1/26

CPC classification number: G06F1/3275 ,  G06F1/266 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3234

Abstract: In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed.

公开(公告)号：US09535487B2

公开(公告)日：2017-01-03

申请号：US14855553

申请日：2015-09-16

Applicant: Intel Corporation

Inventor： Krishnakanth V. Sistla ,  Jeremy Shrall ,  Stephen H. Gunther ,  Efraim Rotem ,  Alon Naveh ,  Eliezer Weissmann ,  Anil Aggarwal ,  Martin T. Rowland ,  Ankush Varma ,  Ian M. Steiner ,  Matthew Bace ,  Avinash N. Ananthakrishnan ,  Jason Brandt

IPC: G06F1/26 ,  G06F1/32

CPC classification number: G06F1/3275 ,  G06F1/266 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3234

Abstract: In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括具有核心的处理器和用于控制处理器的电源管理特征的功率控制器。 功率控制器可以从核心接收能量性能偏差（EPB）值，并根据该值访问功率性能调谐表。 使用表中的信息，可以更新电源管理功能的至少一个设置。 描述和要求保护其他实施例。

公开(公告)号：US09501299B2

公开(公告)日：2016-11-22

申请号：US14306014

申请日：2014-06-16

Applicant: Intel Corporation

Inventor： Ameya Ambardekar ,  Avinash N. Ananthakrishnan ,  Ian M. Steiner

IPC: G06F1/00 ,  G06F9/445 ,  G06F1/32 ,  G06F9/48

CPC classification number: G06F9/44505 ,  G06F1/32 ,  G06F9/4893 ,  Y02D10/24

Abstract: A processor may include a cause agnostic frequency dither filter (FD filter), which may cause reduction in the frequency transitions while maintaining the performance levels. The FD Filter may minimize the performance loss, which may otherwise accrue from these frequency transitions, while trying to maximize the peak frequency of the processor. The FD filter may determine a minimum and maximum limit, which may be used by a power management unit (PMU) to restrict the number of frequency transitions to be within a specified threshold. The FD filter may determine the maximum and minimum limits based on transition data stored in internal tables captured during one or more time windows (or observation windows). Based on an average system behavior, the PMU may either apply the minimum or the maximum limit over the subsequent time window.

Abstract translation: 处理器可以包括原因不可知的频率抖动滤波器（FD滤波器），其可以导致频率转换的降低，同时保持性能水平。 在尝试使处理器的峰值频率最大化时，FD滤波器可以最小化由这些频率转换产生的性能损失。 FD滤波器可以确定最小和最大限制，其可以被功率管理单元（PMU）用来将频率转换的数量限制在规定的阈值内。 FD滤波器可以基于存储在一个或多个时间窗口（或观察窗口）中捕获的内部表格中的转换数据来确定最大和最小限制。 基于平均系统行为，PMU可以在随后的时间窗口中应用最小或最大限制。

公开(公告)号：US09405351B2

公开(公告)日：2016-08-02

申请号：US13716712

申请日：2012-12-17

Applicant: Intel Corporation

Inventor： Ankush Varma ,  Krishnakanth V. Sistla ,  Ian M. Steiner ,  Vivek Garg ,  Chris Poirier ,  Martin T. Rowland

IPC: G06F1/26 ,  G06F1/32 ,  G06T1/20 ,  G06F13/00 ,  G06F9/50 ,  G06F15/173

CPC classification number: G06F1/324 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/329 ,  G06F9/5044 ,  G06F9/505 ,  G06F13/00 ,  G06F15/17325 ,  G06T1/20 ,  Y02D10/126

Abstract: In an embodiment, a processor includes a core to execute instructions, uncore logic coupled to the core, and a power controller to control a power consumption level. The power controller is configured to determine an activity level of the processor and responsive to this level, to generate a request for communication to a second processor coupled to the processor to request frequency coordination between the processors. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器包括执行指令的核心，耦合到核心的非逻辑逻辑以及用于控制功耗水平的功率控制器。 功率控制器被配置为确定处理器的活动级别并响应于该级别，以产生与耦合到处理器的第二处理器通信以请求处理器之间的频率协调的请求。 描述和要求保护其他实施例。

公开(公告)号：US20160187952A1

公开(公告)日：2016-06-30

申请号：US14582741

申请日：2014-12-24

Applicant: Intel Corporation

Inventor： Corey D. Gough ,  Ian M. Steiner ,  Krishnakanth V. Sistla

IPC: G06F1/28 ,  G06F13/42

CPC classification number: G06F1/28 ,  G06F1/3228 ,  G06F13/4282 ,  Y02B70/12 ,  Y02B70/123 ,  Y02D10/14 ,  Y02D10/151

Abstract: A method is provided for controlling a link. This may include determining a condition of a first device coupled to the link, receiving, at the first device, a request for a specific link state from a second device coupled to the link, and determining a power state of the link based on the determined condition of the first device.

Abstract translation: 提供了一种用于控制链接的方法。 这可以包括确定耦合到链路的第一设备的状况，在第一设备处从耦合到链路的第二设备接收对特定链路状态的请求，以及基于所确定的链路来确定链路的功率状态 第一个设备的状态。